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Operational Amplifiers
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1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 4911
Operational Amplifiers Fifth edition
George Clayton and Steve Winder
OXFORD AMSTERDAM BOSTON LONDON NEW YORK SAN FRANCISCO SINGAPORE SYDNEY TOKYO
PARIS
SAN DIEGO
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Newnes An imprint of Elsevier Science Linacre House, Jordan Hill, Oxford OX2 8DP 200 Wheeler Road, Burlington, MA01803
First published by NewnesButterworth 1971 Second edition 1979 Reprinted by Butterworths 1981, 1982, 1983, 1985, 1986 Third edition 1992 Fourth edition 2000 Fifth edition 2003 © Copyright George Clayton and Steve Winder, 2003, All rights reserved The right of George Clayton and Steve Winder to be identified as the authors of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1998. No part of this publication may be reproduced in any material form (including photocopying or storing in any medium by electronic means and whether or not transiently or incidentally to some other use of this publication) without the written permission of the copyright holder except in accordance with the provisions of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London, England W1T 4LP. Applications for the copyright holder’s written permission to reproduce any part of this publication should be addressed to the publishers British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN 07506 5914 9 Typeset by Newgen Imaging Systems (P) Ltd., Chennai, India Printed and bound in Great Britain
For information on all Newnes publications visit our website at www.newnespress.com
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Contents Preface Acknowledgements
ix x
1 Fundamentals
1.1 1.2 1.3 1.4 1.5
Introduction The ideal opamp Feedback and the ideal opamp More examples of the ideal opamp at work Opamp packages Exercises
1 2 2 4 8 9
2 Real opamp performance parameters
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11
Opamp input and output limitations Limitations in gain, and input and output impedance Real opamp frequency response characteristics Smallsignal closedloop frequency response Closedloop stability considerations Frequency compensation (phase compensation) Transient response characteristics Full power response Offsets, bias current and drift Common mode rejection ratio (CMRR) Noise in opamp circuits Exercises
11 13 19 22 25 28 37 44 45 49 50 59
3 Analogue integrated circuit technology
3.1 3.2 3.3
Voltage feedback opamps Comparison of voltage feedback opamps Current feedback opamps Exercises
64 69 73 81
4 Applications: linear circuits
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8
Introduction Voltage scaling and buffer circuits Voltage summation Differential input amplifier configurations (voltage subtractor) Current scaling Voltagetocurrent conversion Voltage regulators AC amplifiers Exercises
82 83 87 88 93 99 103 106 107
5 Logarithmic amplifiers and related circuits
5.1 5.2
Amplifiers with defined nonlinearity Synthesized nonlinear response
109 110
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5.3 5.4 5.5 5.6 5.7
Logarithmic conversion with an inherently logarithmic device Logarithmic amplifiers: practical design considerations Some practical log and antilog circuit configurations Log–antilog circuits for computation A variable transconductance four quadrant multiplier Exercises
113 121 131 139 141 144
6 Integrators and differentiators
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9
The basic integrator Integrator run, set and hold modes Integrator errors Extensions to a basic integrator Integrator reset AC integrators Differentiators Practical considerations in differentiator design Modifications to the basic differentiator Exercises
146 147 148 155 160 162 163 165 168 168
7 Comparator, monostable and oscillator circuits
7.1 7.2 7.3 7.4 7.5 7.6
Comparators Multivibrators Sine wave oscillators Waveform generators The 555 timer The 8038 waveform generator Exercises
171 175 183 187 192 195 198
8 Sensor interface, analogue processing and digital conversion
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14
Sensor interface circuits Hot wire anemometer with constant temperature operation Temperature measurement using a thermocouple Light sensitive switching Sensing analogue light levels Interfacing linear Hall effect transducers (LHETs) Precise diode circuits Fullwave rectifier circuits Peak detectors Sample and hold circuits Voltagetofrequency conversion Frequencytovoltage conversion Analoguetodigital converter (ADC) Digitaltoanalogue converter (DAC) Exercises
199 205 206 207 208 208 209 211 213 215 218 218 220 223 228
9 Active filters
9.1 9.2 9.3 9.4 9.5
Introduction Passive filters Active filters Active filters using operational amplifiers (opamps) Choosing the frequency response of the lowpass filter
230 230 237 241 241
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9.6 9.7 9.8 9.9 9.10
Choosing the frequency response of the highpass filter Bandpass filters using the state variable technique Band reject filter (notch filter) Phase shifting circuit (allpass filter) Filter design Exercises
246 248 251 252 253 265
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12
Opamp selection and design specification Selection processes Attention to external circuit details Avoiding unwanted signals Ensure closedloop stability Offset nulling techniques Importance of external passive components Avoiding fault conditions Modifying an opamp’s output capability Speeding up a low drift opamp Single power supply operation for opamps Voltage regulator circuits Exercises
267 268 270 271 275 277 280 282 284 289 291 293 298
Answers to exercises
300
Appendix A1 Operational amplifier applications and circuit ideas Appendix A2 Gain peaking/damping factor/phase margin Appendix A2.1 Damping factor and phase margin Appendix A3 Effect of resistor tolerance on CMRR of one amplifier differential circuit Appendix A3.1 CMRR of one amplifier differential circuit due to noninfinite CMRR of operational amplifier Appendix A3.2 Overall CMRR due to resistor mismatch and
304 316 317
noninfinite CMRR of operational amplifier
320 321
Appendix A4 Instrumentation transducers A4.1 Introduction A4.2 Resistance strain gauges A4.3 Platinum resistance temperature detectors A4.4 Thermistors A4.5 Pressure transducers A4.6 Thermocouples A4.7 Linear variable differential transformers (LVDT) A4.8 Capacitive transducers A4.9 Tachometers A4.10 Electromagnetic flowmeters A4.11 Hall effect transducers A4.12 Opto transducers Appendix A5 Integrated circuit datasheets
322 323 323 323 325 327 327 328 329 329 329 330 330 331 333
Bibliography
382
Index
383
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Preface Operational amplifiers have been in use for many years. Originally they were built using discrete transistor circuits, but the development of the integrated circuit (IC) has revolutionized analogue circuit design. The operational amplifier was one of the first analogue integrated circuits, because of its usefulness as a building block in many circuit designs. The popularity of the operational amplifier has resulted in a shortened name ‘opamp’ to be commonplace. The term opamp will be used extensively in this book. The opamp’s popularity stems from its versatility. It is a highgain DC amplifier that has differential inputs; the output voltage is the voltage difference between the two inputs multiplied by the gain. Passive components can be used to provide feedback, and this controls the gain and function of the opamp circuit overall. Passive negative feedback components result in a linear response, i.e. the output is proportional to the input. Passive positive feedback results in switching or oscillation. Sometimes active components such as transistors and diodes are used in the feedback loop to give a nonlinear response; typical applications are logarithmic amplifiers or precision rectifiers. My interest in opamp circuits began while I was an apprentice technician. One of the first books that I bought was Clayton’s Operational Amplifiers (first edition). It is therefore fitting that I should be asked by the publisher to edit the fifth edition. In my previous employment as a circuit design engineer for British Telecom, and now as a field applications engineer for Supertex Inc., I have used opamps in hundreds of circuits. For me, one valuable application is in active filter circuits (refer to Chapter 9 and to my book, Analog and Digital Filter Design, ISBN 0–7506–7547–0). In this fifth edition of Operational Amplifiers I have added more on active filters, especially gyrator and frequencydependent negative resistance circuits. Throughout the book I have updated and added material, where appropriate. This includes the important practical guidelines about passive components used in opamp circuits. Although placed near the end of the book, in Chapter 10, this information is important and should not be overlooked. Steve Winder, 2002
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Acknowledgements Figures 2.1, 2.3, 2.30, 3.4–3.9, 4.22–4.25, 7.25, 7.29, 9.30, 9.31, 9.36, 9.37, 10.26 and 10.28 were obtained from IMSI’s MasterClips® and MasterPhotos™ Premium Image Collection, 1895 Francisco Blvd East, San Rafael, CA 949015506, USA. Appendix 5 is reproduced with the permission of Maxim Integrated Products Inc. Maxim is not responsible for any errors or omissions in the reproduction of these data sheets. Before using any information in these data sheets for design purposes, please contact Maxim to ensure you have the current version.
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1 Fundamentals The term ‘operational amplifier’ describes an important amplifier circuit that can form the basis of audio and video amplifiers, filters, buffers, line drivers, instrumentation amplifiers, comparators, oscillators, and many other analogue circuits. The operational amplifier is commonly referred to as an opamp. Although the opamp circuit can be designed from discrete components, it is almost always used in integrated circuit (IC) form. The opamp is a simple building block. It has two inputs, one is called the inverting input (often labelled ) and the other is called the noninverting input (often labelled ). Usually opamps have a single output, but special opamps used in radio frequency circuits have two outputs. Only single output devices will be described in detail, and the symbol used in circuit diagrams is shown in Figure 1.1. The opamp also has two power supply connections, one for the positive rail and one for the negative rail. Many opamp circuits have a midrail supply connected to earth, although the opamp itself has no specific midrail supply connection. Some opamps are specifically designed for single supply operation, and more details of these are provided later. The opamp is a high gain DC amplifier (the DC gain is usually > 100 000; or > 100 dB). With suitable capacitive coupling, the opamp is used in many AC amplifier circuits. The output voltage is simply the difference in voltage between the inverting and noninverting inputs, multiplied by the gain. Thus, the opamp is a differential amplifier. If the inverting () input has the higher potential, the output voltage will become more negative. If the noninverting () input has the higher potential, the output will become more positive. Since the gain is very high, the differential voltage between the input terminals is usually very small. The opamp must have feedback in order to perform useful functions. Most designs use negative feedback to control the gain and to provide linear operation. Negative feedback is provided by components, such as resistors, connected between the opamp’s output and its inverting () input. Nonlinear circuits, such as comparators and oscillators, use positive feedback by having components connected between the opamp’s output and its noninverting () input. It is not essential that the user of opamps is familiar with the details of their internal circuits. However, a little knowledge of the internal circuits does help understanding, particularly the input and output circuits. The user should understand the function of the external terminals provided by the manufacturer. In order to be able to select the best amplifier for a particular application, the user should be familiar with the terms used to specify the opamp’s performance.
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1.2 The ideal opamp
When analysing feedback circuits, it is convenient to assume that the amplifier has certain ideal characteristics. ●
● ● ●
● ●
1.3 Feedback and the ideal opamp
(a)
The output of the ideal differential input amplifier depends only on the difference between the voltages applied to the two input terminals. The performance is entirely dependent on input and feedback networks. No current flows into the amplifier input terminals. The frequency response extends from zero to infinity, ensuring a response to all DC and AC signals, with zero response time and no phase change with frequency. The amplifier is unaffected by the load. When the input signal voltage is zero, the output signal will also be zero – regardless of the input source resistance.
There are two basic ways of applying feedback to an opamp: Figure 1.2(a) shows the inverting configuration, the noninverting configuration being illustrated in Figure 1.2(b). In both circuits, the signal fed back from the output to the input is proportional to the output voltage. Feedback takes place via the resistor R2 connected between the output and the inverting input terminal of the amplifier. Phase inversion through the amplifier ensures that the feedback is negative. The action of both circuits may be understood if a small positive voltage e is assumed to exist between the differential input terminals of the amplifier. The opamp’s output voltage will be equal to the negative supply rail, because of the infinite gain. The signal fed back will be in opposition to e, so forcing the differential input voltage towards zero. Now suppose that e is a small negative voltage. The opamp’s output voltage will be equal to the positive supply rail and feedback is in opposition to e. Again, this forces the differential input voltage towards zero. Thus, negative feedback always forces the differential input voltage to be zero. This is an extremely important point and is worth restating in an alternative form. When the opamp’s output is fed back to the inverting input terminal, the output voltage will always take on that value required to drive
(b)
Figure 1.2 Two basic feedback circuits
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the differential input voltage to zero. For an ideal opamp having infinite gain, the error voltage e is zero. In the case of a practical opamp having large but finite gain, the error voltage e is small but nonzero. The effect of this error voltage will be discussed in the next chapter. A second basic aspect of the ideal circuit follows from the assumed infinite input impedance of the amplifier. In the circuit of Figure 1.2(a), no current can flow into the opamp so that any current arriving at the point X, as a result of an applied input signal, must flow through the feedback path R2. If instead of the single resistor R1 connected to the inverting input terminal there are several alternative signal paths, the sum of these several currents arriving at point X must flow through the feedback path. It is for this reason that the phaseinverting input terminal of an operational amplifier (point X) is sometimes referred to as the amplifier summing point. The two basic aspects of ideal performance are called the summing point restraints; they are so important that they are repeated again. 1. When negative feedback is applied to the ideal amplifier, the differential input voltage is zero. 2. No current flows into either input terminal of the ideal amplifier. The two statements form the basis of all simplified analyses of operational feedback circuits; we use them to derive closedloop gain expressions for the circuits of Figure 1.2. In Figure 1.2(a), the noninverting input is connected to earth. But with negative feedback, the inverting input has the same potential as point X, so this is known as a ‘virtual earth’. Thus the current Ii flowing through R1 is found simply by dividing the input voltage by the resistance of R1. An alternative expression is to say the input voltage is Ii times the value of R1. Since no current flows into the opamp input, the currents through R1 and R2 are equal. The output voltage is the negative product of the Ii times the value of R2. The gain (amplification, or A) is given by dividing the output voltage by the input voltage. This is
A
Ii R2 Ii R1
The current Ii can be cancelled to give A
R2 R1
If R2 is less than R1, fractional gains are possible. In the case of the noninverting amplifier of Figure 1.2(b), the voltage at both inputs must be equal. No current flows into either of the opamp’s inputs, so potential divider R1 and R2 determine the voltage at the inverting input. So voltage ei eA applied to the noninverting input causes the output voltage to become positive until the fraction at the inverting input is equal. The fraction is given by the expression:
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eB
eo R1 (R1 R2 )
Feedback forces the two inputs to have an equal potential, so eA eB eA ei
eo R1 (R1 R2 )
The gain is eo/ei, so transposing the equation we get: A
eo R1 R2 ei R1
A1
R2 R1
Notice that the gain can never be less than 1. A short circuit between the output and the inverting input creates a buffer with unity gain. In theory, this buffer has infinite input impedance and zero output impedance. The inverting and noninverting amplifiers have two main differences. The first difference is the sign of the closedloop gain. More important is the difference in effective input resistance that they present to the signal source ei. The effective input resistance of the ideal inverter measured at the amplifier summing point is zero. Feedback prevents the voltage at this point from changing; the point acts as a virtual earth. Note that any current supplied to this point does not actually flow to earth but flows through the feedback path R2. The resistor R1 thus determines the input current, Ii, in Figure 1.2(a). The input resistance presented to the signal source is equal to the value of R1. Consider the noninverting circuit Figure 1.2(b) where the only connection to the noninverting pin is the signal source. An ideal opamp in this circuit takes no current from the signal source and thus has infinite input impedance. The simple closedloop expressions show that, in the ideal case, the gain depends only on the values of series and feedback components, not on the amplifier itself. Real amplifiers introduce departures from the ideal, and these are conveniently treated as errors. Errors can be made very small and one of the main features of the opamp approach to analogue circuit design is the accuracy with which it is possible to set gain and impedance values.
1.4 More examples of the ideal opamp at work
The ideal opamp serves as a valuable starting point for a preliminary analysis of opamp circuits. In this section we present a few more examples illustrating the usefulness of the ideal opamp concept. Once the significance of the summing point restraints are firmly understood, ideal circuit analysis involves little more than the intelligent use of Ohm’s law. Remember that the ideal differential input opamp, with negative feedback, will try to keep the differential input voltage close to zero. The output voltage takes on the value required to achieve this. In doing so, it causes all currents arriving at the inverting input to flow through the feedback resistor.
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1.4.1 The ideal opamp acts as a currenttovoltage converter An ideal opamp can act as a currenttovoltage converter. In the circuit of Figure 1.3, the ideal amplifier maintains its inverting input terminal at earth potential and forces any input current to flow through the feedback resistance. Thus Iin If and eo IinRf.
Figure 1.3 An ideal opamp acts as a currenttovoltage converter Notice that the circuit provides the basis for an ideal current measurement. It introduces zero voltage drop into the measurement circuit. The effective input impedance of the circuit, measured directly at the inverting input terminal, is zero.
1.4.2 The ideal opamp adds voltages or currents independently The principle involved in the currenttovoltage converter circuit of Figure 1.3 may be extended. In the ideal opamp circuit of Figure 1.4(a) the opamp forces the sum of the several currents arriving at the inverting input to flow through the feedback path (there is no where else for them to go). The inverting input terminal is forced to be at earth potential (a ‘virtual earth’) and the output voltage is thus: eo [I1 I2 I3] . Rf
(a)
(b)
Figure 1.4 An ideal opamp adds currents and voltages independently
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In Figure 1.4(b) a number of input voltages are connected to resistors which meet at the inverting input terminal. The ideal opamp maintains the inverting input at earth potential, thus input current is independently determined by each applied input voltage and series input resistor. The sum of the input currents is forced to flow through R2 and the output voltage must take on a value that is equal to the sum of the input currents multiplied by R2. 1.4.3 The ideal opamp can act as a voltagetocurrent converter In maintaining its differential input voltage at zero, the amplifier shown in the circuit of Figure 1.5 forces a current I ein/R to flow through the load in the feedback path. The value of this current is independent of the nature or size of the load.
1.4.4 The ideal opamp can act as a perfect buffer Figure 1.5 An ideal opamp can act as a voltagetocurrent converter
In the circuit of Figure 1.6 the amplifier output voltage must take on a value equal to the input voltage in order to force the differential input signal to zero. The ideal circuit has infinite input impedance, zero output impedance and unity gain, and acts as an ideal buffer stage.
1.4.5 The ideal opamp can act differentially as a subtractor The circuit shown in Figure 1.7 illustrates the way in which an opamp can act differentially as a subtractor.
Figure 1.6 An ideal opamp can act as an ideal unity gain buffer
Figure 1.7 An ideal opamp can act as a subtractor
The voltage at the inverting input terminal is (by superposition): e– e2
R2 R1 eo R1 R2 R1 R2
The voltage at the noninverting input is:
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e e1
R2 R1 R2
The opamp forces e e Thus e2
R2 R1 R2 eo e1 R1 R2 R1 R2 R1 R2
or, eo
R2 [e – e ] R1 1 2
1.4.6 The ideal opamp can act as an integrator In the circuit of Figure 1.8, negative feedback is applied by the capacitor C connected between the output and the inverting input terminal. The amplifier output voltage acting via this capacitor maintains the inverting input terminal at earth potential and forces any current arriving at the inverting input terminal to flow as capacitor charging current.
Figure 1.8 An ideal opamp acts as an integrator
Thus: Iin
em dV C C R dt
The output voltage is equal in magnitude but opposite in sign to the capacitor voltage. Therefore: de em C 0 R dt e0
1 CR
ein dt
The output is proportional to the integral with respect to time of the input voltage.
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8 Operational Amplifiers
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1.4.7 Limitations of the ideal opamp concept Real opamps have characteristics that approach those of an ideal opamp, but do not quite attain them. They have an openloop gain, which is very large (in the region of 106) but not infinite. They have a large, but finite, input impedance. They draw small currents at their input terminals (bias currents). They require a small differential input voltage to give zero output voltage (the input offset voltage). And they do not completely reject common mode signals (finite common mode rejection ratio, or CMRR). In our discussion of ideal opamp circuits no mention has been made of frequency response characteristics. Real amplifiers have a frequency dependent gain, which can have a marked effect on the performance of opamp circuits. The above features of real opamps cause the performance of circuits to differ from that predicted by an analysis based upon the assumption of ideal amplifier performance. In many respects the differences between real and ideal behaviour are quite small. In some aspects of performance, particularly those involving frequency dependent performance parameters, the differences are significant. Chapter 2 presents detailed discussions about the parameters that are usually given on the data sheets of practical opamps. Knowledge of these parameter values can be used to predict the behaviour of practical circuits.
1.5 Opamp packages
Inexpensive integrated circuit opamps are available, which are easy to use and allow working circuits to be built rapidly. The newcomer to opamps is strongly advised to build a few of the basic opamp circuits and practically evaluate their performance. This forms a useful learning and familiarization exercise, which is worth performing before delving more deeply into the finer aspects of opamp performance. A preliminary practical evaluation of opamp applications is most conveniently carried out using a generalpurpose opamp type. There are several generalpurpose amplifier types to choose from, such as the Texas Instruments TL071 or TLE2027. As a user of opamps, it is not necessary to have a detailed knowledge of their internal circuitry. Fortunately most generalpurpose opamps are pin compatible. It is the function of the external pin connections that the opamp user is primarily concerned. The most common packages for opamps are an 8pin dualinline plastic package (known as DIL8) and its surface mount equivalent, SO8. Smaller surfacemount packages are available, these include the SOT235 shown in Figure 1.9. Dual opamps, where two opamps are housed in the same package are available in 8pin and 14pin DIL or surfacemount packages. Quad opamps, where four opamps are housed together, are available in 14pin DIL and surfacemount packages. Opamps are commonly used with dual power supplies. Input and output voltages are measured with respect to the potential of the power supply common terminal, which acts as the zero signal reference point or ‘earth’. The use of dual supplies allows input and output voltages to swing both positive and negative with respect to the zero reference point.
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SOT235
DIL8
SO8
Figure 1.9 Opamp packages Figure 1.10 shows the circuit connections which are required to make a practical form of the inverting amplifier circuit previously described in Section 1.3. Amplifier pins not shown in Figure 1.10 should be left with no connections made to them – their function will be described later.
Figure 1.10 Opamp connections Particular care, however, should be taken to ensure that the power supplies are connected to the correct pins, as incorrect power supply connections can permanently damage an amplifier. Input signals should not be applied to an amplifier before power supplies are switched on, as application of input signals with no power supplies connected can damage an amplifier.
Exercises
1.1 Give component values and sketch diagrams of operational amplifier circuits for the following applications. Assume ideal opamp performance. (a) An amplifier voltage gain 5 and input resistance 100 k. (b) An amplifier voltage gain 20 and input resistance 2 k.
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(c) An amplifier voltage gain 100 with ideally infinite input resistance. (d) An integrator with input resistance 100 k and circuit performance equation eo 100 ein dt (e) A circuit which when supplied by an input signal of 2 V will drive a constant current of 5 mA through a variable load resistor. 1.2 Find the value of the amplifier output voltage for each of the circuits given in Figure 1.10. In all cases assume that the operational amplifier behaves ideally.
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2 Real opamp performance parameters There are many different opamps to choose from. There are also different technologies such as CMOS, BiFET and bipolar. And bipolar can be separated into voltage feedback or current feedback types. Hence, some consideration of each device’s performance parameters is needed. Selection of the best opamp for a particular application is a problem, especially for the new user of opamps. When first studying manufacturers’ catalogues, the designer is faced with a huge variety of specifications and different opamp types. The choice of opamp is likely to be governed by economic considerations. A generalpurpose opamp will usually cost less than a device that meets a demanding specification. This is because the manufacturer has to recover his development costs and, since generalpurpose devices sell in greater quantities, these costs are spread over a larger number. The least expensive opamp that will meet the design specifications is usually the one to choose. In order to make this choice the design objectives must be completely defined. The designer must also understand the relationship between published opamp parameters and their effects on overall circuit performance for the intended application. This chapter will describe the various opamp specifications normally included in a manufacturer’s data sheet. The significance of these parameters will be discussed. It is important to understand under exactly what conditions a particular parameter is defined. The important question of opamp selection will be returned to in later chapters when opamp applications have been described. The user should then more clearly appreciate design objectives and the way in which opamp parameters limit their achievement.
2.1 Opamp input and output limitations
The input circuit of an opamp is very often a longtailed pair. The longtailed pair is a pair of transistors coupled together at their emitters (in the case of a bipolar input opamp). The connection between the emitters and the supply rail is through a constant current circuit. If the base of one transistor is biased at a slightly higher potential relative to the other, it will conduct more through its collector; and the other transistor of the pair will conduct correspondingly less. The collector of each transistor is taken to the other supply rail through a resistor or, more commonly, through a constant current generator. Figure 2.1 shows the use of resistors, for simplicity.
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V+ R1
2.1.1 Maximum voltage between inputs
R2 } To next stage
IN+
IN–
The voltage between the input terminals of an opamp is maintained at a very small value, under most operating conditions, by negative feedback. If negative feedback is not used, the differential input voltage may exceed this small value and the output of the opamp will saturate, see Figure 2.2.
Constant current V–
Figure 2.1 Opamp input circuit
Figure 2.2 Idealized transfer curve for an opamp If the circuit design allows the application of several volts between the input terminals, care must be taken to ensure that it does not exceed the maximum allowable value, otherwise permanent damage to the opamp may be caused. Many opamps allow the differential input voltage to be equal to the supply voltage, and others are internally protected against input overload conditions. Where such internal protection is not provided, diodes may be connected externally to the opamp’s input terminals to provide the necessary protection.
2.1.2 Maximum output voltage swing V+
Output
Input V–
Figure 2.3 Opamp output circuit
The output of an opamp usually has two transistors, one connected to the positive rail, and the other connected to the negative rail, see Figure 2.3. This circuit controls the output voltage by increasing the drive on one transistor whilst reducing it on the other. Constant current circuits are used in the base drive of these transistors, so that quiescent supply current (the current with no signal) is minimized. Both transistors in this circuit require a certain voltage between collector and emitter, which limits the maximum output voltage swing. The maximum output voltage swing eo max is the maximum change in output voltage (positive and negative), measured with respect to the midrail supply, that can be achieved without clipping the signal waveform. Values of eo max are quoted for the opamp working into a specified load (sometimes at full rated output current) and with specified values for opamp power supplies. Maximum values for supply voltages are normally specified and should not be exceeded. Values for eo max will be found to be dependent on the supply voltage used. BiFET and CMOS opamps have FET outputs that allow the output voltage to be within 200 mV of the supply voltage, except when operating from high supply voltages.
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2.1.3 Maximum common mode voltage The common mode voltage is the average voltage on the two inputs relative to earth. Ecm
eA eB 2
The maximum common mode voltage, Ecm, is the maximum voltage that can be applied without producing saturation or nonlinearity at the output. Many devices have a common mode voltage range that approaches to within 2 V of the supply rails. Single supply opamps often use input circuits that allow the common mode voltage range to extend to the negative supply rail. In the ideal case, common mode input voltage has no effect on the output. eo AOL(eA eB) In practice, the common mode input voltage does affect the output. If an opamp is to be used under conditions in which excessive common mode voltage may cause damage, protection can be obtained by the use of a suitable pair of zener diodes. The diodes should be connected ‘back to back’ with their anodes joined. The two cathodes should be connected to the two opamp inputs.
2.2.1 Noninfinite openloop voltage gain The openloop voltage gain, AOL, of an opamp may be defined as the ratio change of output voltage change of input voltage The input voltage being that measured directly between the inverting and noninverting input terminals. AOL is normally specified for very slowly varying signals and can in principle be determined from the slope of the nonsaturated portion of the input/output transfer curve (Figure 2.2). The magnitude of AOL for a particular opamp depends on the opamp load and on the value of the power supplies. Values of AOL are normally quoted for specified supply voltages and load. Opamps are never used in an openloop arrangement. They are occasionally used in positive feedback circuits, but much more often in negative feedback circuits that define precise operation. The significance of openloop gain is that it determines the accuracy limits in such applications. An assessment of the quantitative effects of the openloop gain magnitude requires a study of the principles underlying feedback opamp operation. In a negative feedback opamp circuit, a signal is fed back from the output to the input. This feedback opposes the externally applied input signal. The signal that actually drives the input of the opamp results from a subtraction process. The larger the gain of the opamp without feedback (the openloop gain) the smaller is the signal voltage applied between the opamp input
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terminals. If the openloop gain of the opamp is infinite (as assumed for an ideal opamp) negative feedback forces the opamp’s differential input signal to zero. However, with a large but finite openloop gain, a small input signal must exist between the opamp’s input terminals. It is convenient to think of this as an input error voltage, which arises because the real opamp has a finite openloop gain. 2.2.2 Noninfinite input impedance The circuit analysis based on the ideal opamp assumed that no current flowed into the opamp’s input terminals. In practice there is a large, but finite, differential input impedance. Part of this impedance is due to input capacitance and this affects high frequency operation. For most applications it is the input resistance that can affect performance. Opamps with FET inputs have an input resistance in the order of 1012 . Bipolar input devices have a lower resistance, but this is usually greater than 106 . The common mode input resistance to earth is much higher than this, typically 100 times greater (i.e. 108 for a bipolar input device) and can be largely ignored. 2.2.3 Nonzero output resistance Opamps do not have zero ohm output resistance. The output resistance of a typical device is 50 . This resistance restricts the maximum output voltage swing into a low resistance load, where a significant voltage drop takes place across the internal resistance. Feedback can reduce the effects of output resistance, making the opamp generate a larger internal voltage to compensate for any reduction due to the output resistance. With feedback, the effective output impedance is typically less than 1 m. 2.2.4 Effect on a noninverting amplifier The effects of finite openloop gain, finite input resistance and nonzero output resistance will be considered for a noninverting amplifier. To analyse the effects, each parameter will have to be considered separately. First we must find a few general relationships for a noninverting amplifier in terms of the noninfinite openloop gain. A differential input opamp with series negative voltage feedback applied to it is shown in Figure 2.4. The opamp has a differential input voltage, e. The opamp’s output is represented in terms of its Thévenin equivalent circuit. The output behaves like a source of EMF (AOLe) in series with the opamp output impedance. (Note the minus sign simply comes from the assumed positive direction of the differential input signal e.) A voltage, ef, which is directly proportional to the output voltage, eo, is fed back to the inverting input terminal of the opamp (negative feedback): ef eo
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–AOLeε
Figure 2.4 Series voltage feedback The constant of proportionality is called the voltage feedback fraction; it is an important quantity when analysing the effects of feedback. If, in Figure 2.4, we assume Zin >> R1 and neglect the shunting effect of Zin on R1 we may write:
R1/(R1 R2)
(2.1)
Now we can examine the effects of nonzero output impedance. The output voltage of the opamp may be written as: eo AOLe IoZo
(2.2)
It is simply a use of the general equation for the output voltage produced by a loaded source of EMF: Output voltage Open circuit voltage Internal volts drop. e is the difference between the externally applied input signal ei and the feedback signal ef. Note that ef and ei are effectively applied in series to the differential input terminals of the opamp. e ei ef
(2.3)
Substitution for e in equation 2.2 gives: eo AOL(ei ef) IoZo Substituting ef eo and rearrangement gives: eo
AOL Zo e –i 1 AOL i o 1 AOL
(2.4)
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According to equation 2.4, the circuit behaves like an amplifier with opencircuit gain AOL/(1 AOL) and output impedance Zo/(1 AOL). These are the closedloop parameters for the circuit. Thus: AOL 1 1 AOL
ACL
and ZoCL
1 1 1 AOL
(2.5)
Zo 1 AOL
(2.6)
Note that if AOL is very large, the quantity
1
1 AOL is as near unity as makes no difference and the closedloop gain is determined almost entirely by the value of the feedback fraction. The closedloop output impedance is made very small (i.e. output voltage little affected by loading). The product of the feedback fraction and the openloop gain is the gain around the feedback loop and it is called the loop gain. Loop gain, AOL is a most important parameter in determining the quantitative effects of feedback. To see the effect of feedback on the output impedance, suppose that 0.1, so that ACL 10. An opamp with Zo 50 and openloop gain AOL 106 will have a closedloop output impedance of 1
ZoCL
50 0.5 m 1 105
At high frequencies the openloop gain reduces, which causes the output impedance to rise. Let us now derive an expression for the input impedance of the circuit. Note that ef is applied in opposition to ei (effectively it is series feedback) and tends to oppose any current into the circuit. Series negative feedback may thus be expected to increase effective input impedance. We write: ei ef e eo e But eo – AOLe
ZL (assuming R2 >> ZL) Zo ZL
Substitution gives:
ei – e 1 AOL Now ZinCL But –
ZL Zo ZL
ei e ZL – 1 AOL Iin Iin Zo ZL
e Zin Iin
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Thus ZinCL – Zin 1 AOL
ZL Zo ZL
(2.7)
Series voltage feedback increases input impedance to an extent determined by the loop gain AOL.
2.2.5 Effect on inverting amplifier The effects of finite openloop gain, finite input impedance and nonzero output impedance will be considered for the inverting amplifier. To analyse the effects, each parameter will have to be considered separately. First we must find a few general relationships for a noninverting amplifier in terms of the noninfinite openloop gain, AOL.
If Iin
I⬘ Io
Figure 2.5 Shunt voltage feedback In Figure 2.5, the externally applied input signal voltage es and the output voltage eo are effectively applied in parallel to the opamp’s differential input. The signal e, which drives the differential input, is a superposition of the effects of es and eo. e es
R2 R1 Rs eo R1 R2 Rs R1 R2 Rs
(2.8)
It is assumed that Zin >> R1 Rs and that Zo fc, the response is asymptotic to the line AOL(jf) AOL(fc/f ) which has a slope of 20 dB/decade change in frequency. For each ten times increase in frequency the magnitude decreases by 1/10, or a change of 20 dB. (Note that a slope of 20 dB/decade is sometimes expressed as 6 dB per octave; it goes down by 6 dB for each doubling of the frequency.) Gain attenuation with increase in frequency is referred to as the rolloff in the frequency response. The two straight lines intersect at the frequency f fc and at this frequency AOL(jf) AOL/√2: the response is thus 3 dB down when f fc. The frequency fc is sometimes referred to as the 3 dBbandwidth limit. The phase/frequency characteristic associated with equation 2.12 is determined by
– tan–1
f fc
(2.14)
At f > fc, → 90°. The Bode phase approximation approximates the phase shift by the asymptotic limits of 0° at 1/10 of fc and 90° at 10 times fc. The asymptotes are connected by a line whose slope is 45° per decade of frequency as shown in Figure 2.6. The errors involved in using the straightline approximation for the magnitude and phase behaviour of equation 2.12 are tabulated in Figure 2.6. Opamp data sheets normally give values of AOL and the unity gain frequency f1, which is the frequency at which the openloop gain has fallen
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A OL ( jf )
approximation
–90°
Figure 2.6 First order lowpass magnitude and phase response and Bode approximations to 0 dB because of openloop rolloff. In the case of opamps which exhibit a first order frequency response, with a 20 dB per decade rolloff down to unity gain, the frequency f1 is related to the 3 dB bandwidth frequency fc by the expression fc f1/AOL. Frequency response characteristics are readily plotted from knowledge of AOL and f1. The Bode magnitude approximations are obtained by simply drawing two straight lines, one horizontal line at the value of AOL and the second through f1 with a slope of 20 dB/decade. The two intersect at the frequency fc. Bode diagrams are useful in evaluating the frequency response characteristics of cascaded gain stages. The gain of a multistage opamp is obtained as the product of the gains of the individual stages, but since gain is represented logarithmically in Bode plots, the overall response may be determined by linearly adding the Bode plots for the separate stages as shown in Figure 2.7. Note that the final rolloff and limiting phase shift depend upon the number of gain attenuating stages. Two stages give a final gain rolloff of
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Figure 2.7 Frequency response of cascaded gain stages 40 dB/decade and a limiting phase shift of 180°; three stages give a gain rolloff of 60 dB/decade and a 270° phase shift.
2.4 Smallsignal closedloop frequency response
The desirable characteristics of opamp circuits stem from the use of negative feedback. The quantitative effects of negative feedback are related to the loop gain AOL. Real opamps exhibit a frequency dependent AOL, and in some applications the feedback fraction is also frequency dependent. Therefore, practical opamp circuits have a frequency dependent loop gain and this has a marked effect on closedloop performance. Frequency dependence implies both a magnitude change and a phase change with frequency. In a circuit using negative feedback, it only needs a phase shift of 180° in the feedback loop to make the circuit apply positive feedback; this can cause serious problems. An opamp feedback circuit will produce selfsustained oscillations if the phase shift in the feedback loop reaches 180° while the magnitude of the loop gain is greater than unity. This should not be allowed to happen. Phase shifts in the feedback loop of greater than 90° but less than 180° will not result in sustained oscillations. However, they can cause a frequency response that peaks up at the bandwidth limit, before it rolls off. Associated with this closedloop gain peaking, the circuit will have a transient response that exhibits overshoot and ringing. Transient response refers to the output changes produced in response to a step or squarewave input signal.
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Phase margin is a term used to express the relative stability of a closedloop opamp circuit. The phase margin is the amount by which the phase shift is less than 180° at the frequency where the magnitude of the loop gain is unity. A closedloop circuit with 90° phase margin shows no gain peaking. As the phase margin is reduced, gain peaking becomes noticeable for phase margins of approximately 60° (about 1 dB peaking) and becomes more marked with further reduction in phase margin (20° phase margin gives approximately 9 dB of gain peaking). Most generalpurpose opamps have an openloop frequency response that follows a first order decay characteristic. The openloop gain reduces in proportion to the signal frequency. This ensures that they are unconditionally stable under any value of resistive feedback. This type of response was discussed in the previous section; it has a 20 dB/decade rolloff down to unity gain and the phase shift associated with this never exceeds 90°. The phase margin for any value of resistive feedback is therefore never less than 90°. The gain frequency dependence of the openloop response also affects the closedloop response. The effect on closedloop gain is most conveniently demonstrated in graphical form by sketching the appropriate Bode plots. We look for the effect of AOL on loop gain and then to the effect of loop gain on the gain error factor. We may write:
 AOL(jf) 
AOL(jf) 1 (jf)
Which when expressed in decibel form gives: loop gain (in dB) openloop gain (in dB)
1 (in dB)
(2.15)
That is, the magnitude of the loop gain in decibels at any frequency is equal to the difference between the openloop gain magnitude in decibels and 1/ in decibels. As an example of the graphical approach, consider an opamp with a first order frequency response used with resistive feedback in the follower configuration. The circuit and its Bode plots are illustrated in Figure 2.8. In order to display the frequency dependence of the loop gain we merely superimpose the plot of 1/ (in dB) on the openloop frequency response plot of the opamp. If feedback is purely resistive, as it is here, is independent of frequency and 1/ is a straight line parallel to the frequency axis. In this case, the frequency dependence of the loop gain is entirely due to the frequency dependence of the openloop gain. As the frequency increases there is a reduction in openloop gain, AOL. There is a corresponding decrease in the loop gain, AOL and an increase in the gain error. Remember that gain error is related to the amount by which the gain error factor [1/(1 1/AOL)] differs from unity. If it is required to compute the gain error at frequencies approaching or exceeding the openloop bandwidth fc, the phasor nature of the loop gain
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Figure 2.8 Bode plots show frequency dependence of loop gain must not be forgotten. Let us evaluate the gain error for the circuit of Figure 2.8 at a frequency f 103 Hz. At this frequency, AOL(jf) 20 dB 10, and the phase shift in the loop gain is close to 90°. Thus:
1
1
1 AOL(jf)
1
1
1 –j10
1 0.995 √1 0.01
Compare this with the value obtained by neglecting the phasor nature of the loop gain, which is: 1/(1 1/10) 0.909, a 9% gain error! At the frequency f1′ at which the openloop and 1/ magnitude plots intersect, the magnitude of the loop gain is unity (0 dB). The two plots close at a rate of 20 dB per decade, which is indicative of a 90° phase shift in the loop gain and a remaining 90° phase margin. The magnitude of the gain error at the frequency f1 is: 1/(1 1/j1) 1/√2 The closedloop gain magnitude is thus 3 dB down on its ideal value 1/ at the frequency f1′. f1′ represents the closedloop bandwidth; at frequencies greater than f1′ the magnitude of the closedloop gain approaches the magnitude of the openloop gain. If AOL(o) >> 1, the product of closedloop gain and closedloop bandwidth 1/(f1′) f1 remains constant for different values of . Negative feedback makes the closedloop bandwidth greater than the
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Figure 2.9 Bode plots for inverting adder openloop bandwidth. The greater , the smaller the closedloop gain but the wider the closedloop bandwidth. A second example of the graphical approach used to find closedloop signal bandwidth is illustrated in Figure 2.9. The circuit considered here is an inverting adder application. In this type of circuit the feedback fraction is influenced by the presence of the two input resistors R1 and R2.
Rp Rp Rf
where Rp R1 // R2
R1 R2 R1 R2
Substituting component values gives 1/1000 and 1/ 1000 or 60 dB. 1/ intersects the openloop frequency response at the frequency f1′ 1 kHz. This fixes the closedloop bandwidth at 1 kHz but note that, in this circuit, the closedloop signal gain is not the same as the closedloop gain (1/) since there are two possible input signal paths. The ideal signal gain for the e1 signal is Rf /R1 and is Rf /R2 for the e2 signal. In this particular example R1 R2, so the two gains are equal and the closedloop signal bandwidth is 1 kHz.
2.5 Closedloop stability considerations
Most opamps are internally frequency compensated and have an openloop frequency response with a 20 dB/decade rolloff. A response of this kind, in principle, ensures that the opamp will be closedloop stable under all
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conditions of resistive feedback. However, it is important to be aware that 1111 the use of an internally frequency compensated opamp does not always 2 ensure closedloop stability. 3 Capacitive loading at the output of an opamp, or stray capacitance between 4 the inverting input terminal and earth, can cause phase shifts leading to insta5 bility – even in resistive feedback circuits. In differentiator applications, in 6 which the feedback fraction is deliberately made frequency dependent, an 7 internally compensated opamp exhibits instability. 8 Some opamps exhibit a final rolloff in their openloop frequency response 9 of greater than 20 dB/decade; they are called externally frequency compensated 1011 opamps. These fast rolloff opamps are often used in circuits where both wide 1 closedloop bandwidth and greater than unity gain are required. They require 2 the external connection of a capacitor to make them closedloop stable. 3 The closedloop frequency response obtained with fast rolloff (externally 4 frequency compensated) opamps can be explained using Bode plots. The 5 response is related to the gain error caused by the decaying openloop gain 6 and the associated phase shift. For example, consider an opamp with a 7 response that has three gain stages, each stage having a frequency response 8 with a different cutoff point. The magnitude and phase characteristics of 9 the openloop gain are illustrated in Figure 2.10. 20111 The magnitude and phase characteristics of the loop gain for a particular 1 feedback fraction are obtained by superimposing a plot of 1/ on the open2 loop frequency response plot. With resistive feedback, is frequency 3 independent. The phase shift in the closedloop gain is determined by the 4 phase shift in the openloop gain; this can be found by referring back to 5 the graphs in Figure 2.5. 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 49111 Figure 2.10 Gain magnitude and phase characteristics of opamp with threepole response
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1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 Figure 2.11 Too much feedback gives gain peaking with uncompensated fast rolloff opamps 4 5 6 Phase margin is the amount by which this phase shift is less than 180° at 7 the frequency at which the magnitude of the loop gain is unity (0 dB). Note 8 that increasing results in successively smaller phase margins. Phase margins 9 less than 60° cause the closedloop gain to peak up (see Figure 2.11). The 30111 gain peaking increases as the phase margin is reduced further until, at zero 1 phase margin, the circuit breaks out into sustained oscillations. 2 3 4 2.5.1 Phase margin determines closedloop gain peaking 5 6 The gain peaking occurs as a result of inadequate phase margin and is caused 7 by positive feedback. Positive feedback occurs when the feedback signal has 8 a component that is in phase with the externally applied input signal. If the 9 gain is greater than unity when phase shift in the loop gain reaches 180°, 40111 the circuit oscillates. 1 When considering the extent of the gain peaking (obtained as a result 2 of inadequate phase margin) we must look to the effect of the loop gain 3 magnitude/phase behaviour on the gain error factor. 4 5 AOL(jf) AOL(jf)ej 6 7 8 4911
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The value of the gain error factor may then be expressed as 1 1
1
1
AOL(jf)
1
e j  AOL(jf) 
1 cos jsin 1  AOL(jf)  The magnitude of the gain error factor can then be written as
1
1
1
AOL(jf)
1 2 cos 1  AOL(jf)2  AOL(jf)  1
(2.16)
Since the cosine of angles lying between 90° and 180° is negative we have the possibility of a gain error factor magnitude greater than unity for values of greater than 90°. It is this variation in the gain error factor that is responsible for closedloop gain peaking. Gain peaking usually arises as a result of phase shift with frequency controlled by a single first order function. Here the break frequency is greater than a decade away from other break frequencies. Two situations are illustrated in Figure 2.11. The relationship between closedloop gain peaking and phase margin that is to be expected in a situation of this kind is also shown graphically in Figure 2.12 (see also Appendix A2). In order to assess the phase margin in a particular circuit, the 1/ graph (in dB) is superimposed on the openloop response. The intersection of the two curves gives the frequency f1′ at which the magnitude of the loop gain is unity. The phase shift at this frequency is then determined from the phase/frequency variation in AOL; the phase margin is m 180° . The amount of gain peaking can be found from the graph. Note that the gain peaking in fact occurs at frequencies slightly less than the frequency f1′. However, as the phase margin is reduced, the gain peak increases in amplitude; the frequency at which it occurs moves closer to the frequency f1′.
2.6 Frequency compensation (phase compensation)
Frequency compensation or phase compensation is the name given to the process of tailoring the loop gain magnitude/phase characteristics of a feedback opamp circuit to give an adequate phase margin. Adequate phase margin ensures closedloop stability and freedom from closedloop gain peaking. Bode diagrams are particularly useful in assessing the stability and frequency response of feedback circuits, and examples will be given in terms of their Bode diagrams. Generalpurpose opamps are normally internally frequency compensated and give unconditional stability with all values of resistive feedback. The phase shift in their openloop gain is typically controlled to be 135° or less
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Figure 2.12 Gain peaking versus phase margin for two commonly encountered situations for all frequencies where the openloop gain magnitude is greater than unity, assuring a minimum phase margin of 45° for all values of resistive feedback. Internal frequency compensation gives user convenience at the expense of closedloop bandwidth and speed (slew rate – see later) which would otherwise be available when the opamp is used at higher closedloop gains than unity. It is important to note that even frequency compensated opamps can become unstable if the load is sufficiently capacitive. The internal resistance and the external capacitance cause a phase shift at the opamp’s output terminal. Even though the opamp may have a phase margin of 45° or more, the phase shift at the output can be greater than this and lead to oscillation. This is because feedback is taken from the opamp’s output. An external resistor between the opamp’s output at the load reduces the phase shift at
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the output, and hence in the feedback path. The subject of compensating for capacitive loads and capacitive inputs is discussed further in Section 10.5. Opamps without internal frequency compensation require external frequency compensating components. They allow the user to select a frequency compensating scheme appropriate to the particular closedloop circuit. Closedloop bandwidth, slew rate, full power response and noise performance (see later) are all affected by the frequency compensating method adopted. Compensation methods advocated for different opamp types differ in detail because of internal circuit differences. The general principles involved in frequency compensation are the same for all opamps. Amplifying stages within an opamp can achieve very high gains by using active loads. In many cases the overall gain can be sufficiently large using only two internal voltage gain stages. Opamps of this type are normally frequency compensated by means of a single feedback capacitor connected around the second inverting gain stage in the opamp. The technique requires only small values of frequency compensating capacitor (10 pF–30 pF). Capacitors of this size are small enough to be fabricated on the same integrated circuit chip as the rest of the opamp circuitry. This is the method of internal frequency compensation in generalpurpose opamps: a simplified model of the internal circuit is given in Figure 2.13.
Figure 2.13 Equivalent circuit for frequency compensation
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The differential input stage used in many opamps has a very high gain and a very high output impedance; it provides what is essentially a current drive to the second gain stage. In Figure 2.12, its action is represented by the current generator gme. The second gain stage is inverting; a capacitor connected between input and output of the high gain inverting stage gives that stage the frequency response characteristics of an integrator. Its output voltage is proportional to the integral of the input current. Assuming ideal integrator action for the second stage, its output and the output of the complete opamp has a frequency rolloff that can be approximated as eo
gme j Cf
and the openloop gain rolloff is approximated by AOL(jf) –
gm j 2 f Cf
(2.17)
Equation 2.17 must be made to dominate the overall frequency response. Unity gain frequency compensation requires that the value of Cf be chosen so that the equation brings the openloop gain down to unity at a frequency lower than the break frequency of other gain attenuating stages. Setting AOL(jf) 1 in equation 2.17 and transposing gives equation 2.18. This gives the relationship between the unitygain frequency (f1) and the required unitygain frequency compensating capacitor (C1) as f1 gm/2 C1
(2.18)
In many generalpurpose opamps, the current drive supplied by the first gain stage has a frequency dependence. This is determined by the frequency response of transistors in the first stage, where the break frequency may be a few MHz. Dependent upon the unitygain phase margin required, f1 must be made to have the same order of magnitude. Most generalpurpose monolithic opamp designs have Cf chosen to make f1 typically slightly less than the break frequency of the first stage transistors. Unitygain frequency compensation, although satisfactory, is not strictly necessary when an opamp is used in a circuit where the closedloop gain (1/) is greater than unity. Externally compensated opamps in which the frequency compensating capacitor is user connected permit the designer to apply just sufficient compensation to achieve a desired phase margin. Some internally compensated opamps have a minimum stable gain specified; these devices have a greater gainbandwidth product than would otherwise be achievable with a unitygain stable device. Use of the minimum frequency compensating capacitor, consistent with achieving adequate phase margin, gives a wider closedloop bandwidth than would be obtained if the opamp were unitygain frequency compensated. In applications that are concerned only with slowly varying input signals, a wide closedloop bandwidth is of course not required. In such cases it is often advantageous to restrict closedloop bandwidth (in order to reduce
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noise) by using much greater frequency compensation than is required for closedloop stability. These points are illustrated in Figure 2.14 which shows Bode approximations for the openloop frequency response of a generalpurpose opamp, using values of the frequency compensating capacitor Cf larger than and smaller than the value C1 required for unitygain frequency compensation of the opamp. Adequate phase margin (60° in the case considered in Figure 2.14) requires that the minimum value of Cf be chosen so, for a particular value of B used in the circuit configuration, the magnitude of the loop gain B*AOL is reduced to unity at the frequency f1. Use of equation 2.17 gives
AOL( jf )
R1 R1 + R2
Figure 2.14 Openloop frequency response of opamp with different values of compensation capacitor
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 AOL(jf)
gm 2 f Cf
We require AOL(jf) 1, at f f1 Substituting for f1 from equation 2.23 gives the required minimum value of Cf as Cf C1
(2.19)
Remember that C1 is the value of the frequency compensating capacitor required for unitygain frequency compensation. A typical value of frequency compensating capacitor is 30 pF for unitygain frequency compensation. Lower values can be used for higher closedloop gains. Typically, a 3 pF frequency compensating capacitor can be used if the closedloop gain is 20 dB. There are certain conditions in which the use of minimum values of Cf can lead to instability problems. These are in circuits with large resistor values, or where there is appreciable stray capacitance to earth at the inverting input terminal, or those in which the opamp is expected to drive a capacitive load.
2.6.1 Frequency compensation and slew rate considerations There is a limit to the rate at which the output voltage of an opamp can change; this is called the slew rate. Slew rate is usually expressed in volts per microsecond and is defined as the maximum rate of change of output voltage produced in response to a large input step. The basic mechanism governing slew rate is capacitor charging. The rate of change of voltage, at any point in a circuit, is limited by the maximum current available to charge the capacitance at that point. In many opamp applications it is the charging of the frequency compensating capacitor (internal or external) that sets the output slew rate. For this reason, opamps designed to have low supply current requirements are generally slower and bandwidth limited. The frequency compensating capacitor of an opamp is charged by the output current supplied by the first gain stage in the opamp. The limitation on the charging rate is therefore determined by the first stage output current capabilities, thus: Slew rate
deo dtmax
Io C
(2.20)
where Io is the first stage operating current. Equation 2.20 suggests that increased slew rate may be achieved by simply increasing the first stage operating current, but this is not the case for opamps using bipolar transistor input stages. In normal bipolar transistor opamp
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stages increase in operating current causes a corresponding increase in the transconductance of the stage: Transconductance gm
Io 2kT q
(2.21)
where: k is Boltzmann’s constant, T is temperature in K (Kelvin) and q is electronic charge. Equation 2.21 is a modification of the transconductance equation for bipolar transistors: Transconductance gm
ICq kT
which is ~40 IC V1 at room temperature.Thus for a transistor with a collector current of 1 mA, gm = 40 mA V1 and a VBE change of 1 mV causes a collector current change of 40 A. The value of transconductance is halved in the input stages of an opamp because of the differential input, so a differential input of 1 mV gives rise to an output current of 20 A. Increase in transconductance that accompanies any increase in operating current requires a corresponding increase in Cf in order to set a particular value for f1. Combining equations 2.20 and 2.21 with equation 2.18 gives Slew rate
deo dtmax
2kT 2 f1 q
(2.22)
Slew rate is seen to be independent of input stage current level. Our approximate treatment explains why most internally compensated generalpurpose bipolar input opamps have slew rates of the order of 1 V/ s. Bipolar input opamps that are externally frequency compensated have the same slew rate limitation when compensated down to unity gain. When they are frequency compensated for closedloop gains greater than unity the smaller value of the frequency compensating capacitor which is required gives an increased slew rate. High slew rate bipolar input opamps are available; they feature specialized input stage circuitry which provides increased current output without at the same time giving an increase in the transconductance of the stage. FET input opamps do not have the above limitation on slew rate because unlike bipolar transistors, FETs do not have their transconductance directly dependent upon operating current. FET input opamps normally feature a higher slew rate than bipolar input opamps. 2.6.2 Feedforward frequency compensation A few opamps are suitable for use with feedforward frequency compensation. This technique can provide a significant increase in bandwidth and slew rate over standard lag compensation techniques. In most opamps the first stage provides the greatest single contribution to the overall gain of the opamp, but its frequency response is normally
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rather limited. In feedforward frequency compensation the highgain lowbandwidth first stage is bypassed at the higher signal frequencies and these are fed directly to the wider bandwidth second stage of the opamp. Using this technique, the phase shift at the higher frequencies is primarily due to the wide band stage, and the phase shift due to the highgain lowbandwidth stage is eliminated. The principle underlying the scheme is illustrated in Figure 2.15.
Figure 2.15 Principle of feedforward frequency compensation
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The overall gain due to both stages may be expressed as
AOL(j ) A1(j )
R R
1 j C
A2(j ) Ai(j )
1 1
1 j CR
A2(j )
C is chosen so that when f > 1/2 CR the gain of the first stage has fallen to below unity, making the overall gain approximately that of the second gain stage. The second stage 20 dB/decade rolloff takes the overall gain down to unity. Bode plots of the uncompensated response and the response with feedforward compensation are illustrated in Figure 2.15. Feedforward frequency compensation is only applicable to inverting feedback configurations using externally compensated opamps. 2.6.3 Lead compensation Lead frequency compensation is a technique used to increase the phase margin. A capacitor is included in a feedback loop to introduce a phase lead, compensating for the opamp phase lag, which would otherwise result in insufficient phase margin. A simple way of achieving this is to connect a capacitor Cf in parallel with the feedback resistance. A circuit using this method of lead compensation is shown, together with its associated Bode plots, in Figure 2.16. We write R 1 R 1 j Cf (R1//R2) 1 1 2 1 2 1 R1 1 j Cf R2 R1 1 j Cf R2
At frequencies greater than 1/2 Cf R2 the capacitor introduces a phase lead in the feedback fraction, which approaches 90°. If Cf is chosen so that the frequency 1/2 Cf R2 is a decade below the frequency at which the 1/ and openloop response plots intersect, a phase margin of approximately 90° is obtained. Use of a lead capacitor in parallel with a feedback resistor is a convenient way of getting extra phase margin. It is also a technique that can be used to overcome the effect of stray capacitance between the opamp’s inverting input and earth (see Section 9.5). 2.6.4 Other frequency compensating techniques Techniques other than those described in the above sections are sometimes used for frequency compensation. Whatever technique is used, the same basic principle is involved. Frequency compensation involves attenuating the loop gain magnitude down to unity without, at the same time, introducing an excessive phase shift leading to closedloop instability. Frequency compensation is achieved by simply shunting a signal point in the feedback loop with a capacitor (Figure 2.17). Assuming the output resistance at the signal point is Ro the added capacitor introduces a 20 dB/decade rate of attenuation, which starts at the break frequency 1/2 C1Ro. The maximum phase shift associated with a CR lag network is 90°. The capacitor value must be chosen so that the loop gain magnitude is attenuated down to unity at a frequency lower than other break frequencies of attenuating stages.
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Figure 2.16 Lead compensation Shunting a signal point with a capacitor resistor combination (a lagnetwork) is an alternative technique that allows wider closedloop bandwidths (Figure 2.18). At frequencies above 1/2 C1R1 (the breakback frequency) a network of this kind produces an attenuation R1/(R1 Ro) but the phase shift returns to zero.
2.7 Transient response characteristics
Previous sections have been concerned with factors influencing the smallsignal frequency response characteristics of opamp feedback circuits. Attention is now directed to the factors influencing their behaviour in time, namely their transient behaviour in response to large and small input step or squarewave signals. Students may gain a greater understanding of opamp transient behaviour, and the terminology used to describe it, by performing transient tests. Frequency compensating component magnitude, load capacitance, input
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Figure 2.17 Simple lag compensation with single capacitor
capacitance and any stray feedback capacitance all influence closedloop transient behaviour.
2.7.1 Smallsignal transient response Smallsignal characteristics are those obtained when there are no saturation effects (no slew rate limited output) and the opamp circuit is operating in its linear range. In smallsignal operation circuit relationships are independent of the level of the output voltage and current, and of their previous history. The smallsignal transient behaviour of an opamp feedback circuit is closely related to its smallsignal sinusoidal frequency response. In our previous discussion of smallsignal closedloop frequency response we distinguished between two different closedloop situations.
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Figure 2.18 Frequency compensation with RC shunt
In the first situation, consider a unity gain frequency compensated opamp with resistive feedback. Figure 2.19 illustrates the considerations governing the behaviour of such a circuit. In response to an input step signal the output follows an exponential governed by the relationship Vo Vf [1 – e–t/Tc]
(2.23)
where the time constant TC T1/ and T1 1/2 f1. Notice that TC increases for increasing values of closedloop gain (decrease in ) and decreases for increasing values of the unity gain frequency f1. Rise time is a parameter that is frequently used to characterize the response of an opamp to an input step. Rise time is defined as the time taken for the output to rise between 10 per cent and 90 per cent of its final value. Neglecting
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Figure 2.19 Small signal sinusoidal and transient response for unity gain frequency compensated opamp with resistor feedback the time for the initial 10 per cent rise an approximate expression for rise time can be obtained by substituting Vo 0.9Vf in equation 2.23. Thus, 0.9Vf Vf [1 – e–Tr /Tc] giving Tr /Tc ln (10), where ln (x) is the natural logarithm of x. or Tr ln (10)/2 f (3 dB) Tr ~ 1/[3f (3 dB)] f (3 dB) f1 is the closedloop smallsignal 3 dB bandwidth limit. The second situation is when using a closedloop configuration with a lightly damped transient response. The most commonly encountered closedloop configurations which exhibit a lightly damped transient response are those in which the frequency response is governed by two breaks, and in which the break frequencies are remote
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fc1
Figure 2.20 Lightly damped closedloop response from each other by at least a decade (see Figure 2.20). Systems of this kind have a response that is typical of a second order system. The response equation is obtained by substituting the frequency dependent loop gain expression into the gain error factor (see Appendix A2). A second order system is characterized by parameters called the damping factor and natural frequency fo. A step input, Vst , causes overshoot and ringing. Treating ACLVst as a scaling factor and plotting time in units of ot the normalized step response for different values of the damping factor is plotted in Figure 2.21. The step response shows an increasing overshoot and ringing as the value of the damping factor is successively reduced below unity. The damping factor is related to the break frequencies, governing the frequency response of the opamp by the expression
√fc
2
2√A(o) fc1
The amount of gain peaking to be expected in the smallsignal closedloop frequency response is related to the damping factor by (Appendix A2) P(dB of peaking) 20 log
2 √1 – 1
2
where 1/√2. Note: there is no peaking in the sinusoidal response for > 1/√2.
(2.24)
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Figure 2.21 Second order step response
2.7.2 Overshoot In the case of a lightly damped response ( < 1), the amount by which the first ringing peak exceeds the final value is referred to as overshoot. Expressed as a percentage of the final value Overshoot % 100e
√1– – 2
(2.25)
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2.7.3 Smallsignal settling time Overshoot represents the maximum output transient error following initial rise in response to a stepped input. The time taken by the output to settle within a certain accuracy (settling time) following a transient is often of greater interest. A conservative estimate of the smallsignal settling time for a second order system can be made by finding the smallest value of N which satisfies: 100e
– N
1 – < x % 2
where x% represents a specified accuracy. The settling time is found by substituting N into the following equation: t
N
o √1 – 2
Smallsignal settling time is clearly directly related to the value of the damping factor. For fast settling to a high accuracy, nothing is to be gained by using damping factors less than unity. Although light damping does give a faster initial rise, any ringing prolongs settling time. It is for this reason that designers of fast settling opamps strive to have the openloop frequency characteristic strongly dominated by a single 20 dB per decade rolloff down to unity gain in the openloop frequency response.
2.7.4 Largesignal time response characteristics If the opamp is operating in its nonlinear regions, the smallsignal transient response characteristics discussed in the previous section no longer apply. In this section some of the effects accounting for the difference between small and largesignal characteristics are considered. Slew rate Within an opamp there is inherent semiconductor and circuit capacitance, as well as those added for frequency compensation. There is also load capacitance at the output. The rate of change of voltage at a point in the circuit depends on the available current to charge the capacitance at that point: I dV max dtmax C This mechanism sets an upper limit to the rate at which the output voltage of an opamp can change. Slew rate, usually expressed in V/ s is the parameter that is used to characterize the effect. As discussed in Section 2.7.1 it is often the charging of the frequency compensating capacitor which determines the output slew rate, but there are applications in which the charging of some other circuit capacitance sets the limit, for example large capacitive loads.
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Slew rate is the performance parameter which determines the maximum frequency at which an opamp can give a fullscale sinusoidal output signal, and is one of the important factors in determining large signal settling time. Slew rate determines the maximum operating frequency in such applications as precise rectifiers. Overload recovery An opamp in a saturated overload condition takes a finite time to recover to linear operation. Overload recovery defines the time required for the output voltage to recover to within its rated value from a saturated condition. Saturation takes place when an opamp’s output voltage exceeds its rated value. It also occurs during nonlinear slew with the output within rated limits. Saturation causes charges within the circuit to become unbalanced. These charges must be brought back to equilibrium before the opamp can operate normally. In an opamp circuit required to give a fullscale output step there is a period of recovery which is comparable to the period of slew. The recovery period may be substantially greater if many internal stages are involved. Fast slew rate, therefore, is not by itself a good indicator of a fast settling opamp. Some opamps with extremely large slew rates have excessive recovery time. Large signal settling time Settling time is defined as the time elapsed from the application of a perfect step input to the time when the opamp’s output has reached its final value (within specified tolerances). Largesignal settling time is usually specified for the condition of unity gain and a fullscale output step. The main contributions to settling time are slew rate and overload recovery.
2.8 Full power response
The inability of an opamp’s output voltage to slew faster than a limiting rate can lead to distortion of sinusoidal signals. This is true, even though their amplitude is below the maximum rated output voltage for the opamp. Some manufacturers specify the effect by opamp full power response, fp1, defined as the maximum frequency, measured at unity closedloop gain, for which full output can be obtained at rating load without distortion. An approximate relationship between slew rate and full power response is readily derived if it is remembered that in the case of a sinusoidal signal the maximum rate of change occurs as the signal passes through zero. Consider a sinusoidal output signal with amplitude equal to the rated output voltage Eo and frequency fp: eo Eo sin(2 fpt) deo 2 fp Eo cos(2 fpt) dt
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Slew rate
deo dt
max
2 fp Eo
(2.26)
If the output amplitude is reduced, distortion due to slew rate does not occur until the frequency is increased above fp. Opamp data sheets sometimes give graphs which relate maximum sinusoidal output voltage obtainable without distortion to frequency; they show what is called the power bandwidth of the opamp.
2.9 Offsets, bias current and drift
In circuits where the DC response is important, offset voltages, bias currents and drift have to be taken into account. An opamp is normally required to give zero output voltage (referred to earth – or midrail) when the voltage between its input terminals is zero. When a constant DC input signal is applied, the opamp’s output should remain at a constant voltage. Parameters are defined which indicate how far real opamps depart from this ideal behaviour. In a circuit designed to handle AC signals, a DC path from both inputs to either earth or another DC voltage source is required. A noninverting opamp with a capacitively coupled input signal needs a resistor, between the input and the midrail supply, in order to supply bias current to the noninverting () input. The feedback resistor, between the output and the inverting input, supplies bias current to the inverting () input. An opamp with its input terminals shorted together is found to give a nonzero output voltage or ‘offset’. In some cases, the high gain of the opamp will cause the output voltage to be at one of its saturated levels. It is therefore usual to specify opamp offsets by referring them to the input of the opamp. The input offset voltage, Vio, is defined as that input voltage which would have to be applied in order to cause the opamp output voltage to be zero. It is specified at a particular temperature. All opamps require some small relatively constant current at their input terminals, called an input bias current. In the case of a differential opamp the input bias current, Ib, is defined as the average value (half the sum) of the currents at the two input terminals with the opamp output voltage at zero. It too is specified at a particular temperature. Ideally the currents taken by the two input terminals should be the same under these conditions but in practice some degree of mismatch always exists. The input offset current, Iio, is defined as the difference in the input bias currents to the two input terminals, at a particular temperature. With equal source impedances connected to the two input terminals, it is only this mismatch, or difference current, which causes an offset error. The effects of bias and offset currents tend to overshadow the effects of input offset voltage when the input source impedances are high. Provision is normally made for balancing out the effects of initial opamp offsets by means of a suitable potentiometer. After this adjustment has been made the output voltage of an opamp is still found to change, even though the applied input signal is zero or a constant DC value. This slow change in the output voltage of an opamp is referred to as drift. Drift problems do
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not arise in AC opamps because any DC change in voltage level is effectively blocked off from the output by a coupling capacitor. A specification for the drift in an opamp’s output voltage would, in itself, give little criterion for the selection of an opamp for drift performance. The observed output drift is dominated by drift in the early stages of the opamp, for this is magnified many times by subsequent stages before appearing at the opamp output. It is usual to characterize drift performance by referring the drift to the input; the various contributions to drift are specified by their effects on opamp input offsets.
2.9.1 Temperature drift In opamps, drift with temperature normally represents the largest single source of drift. This causes the biggest errors in many applications. It arises because of the temperature dependence of the characteristics of both active and passive components. Temperature drift may be specified by the temperature coefficients of bias current and input offsets. The coefficients, Ib/T, Iio/T and Vio/T are usually defined as the average slope over a specified temperature range. The drift to be expected for a defined temperature change from ambient is found by multiplying the specified drift rate by the temperature excursion. The drift of bias current, the input offset current and the input offset voltage are generally a nonlinear function of temperature. The drift rates are normally greater at the extremes of temperature.
2.9.2 Supply voltage sensitivity Changes in the opamp’s power supply voltage causes changes in opamp output voltage. The effect is usually specified by the effect of supply voltages on input bias current and input offsets. Supply voltage coefficients, Vio/V, Ib/V and Iio/V are included in most data sheets. In the case of opamps using twin power supplies, the positive and negative supply voltage coefficients will not normally be the same. However, with regulated power supplies, drift due to power supply changes will normally be negligible compared with temperature drift.
2.9.3 Evaluating errors due to input offset voltage and bias current In applications requiring a response down to DC, the opamp input offset voltage and bias current, and their drift coefficients, are usually the limiting performance parameters. A general method for evaluating offset errors will now be described. The use of error signal generators at the input of an otherwise ideal opamp (see Figure 2.22) conveniently represents offset voltage and bias current. Combining the effects of the separate error generators into one single generator provides further simplification. The effects of bias current are expressed
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Figure 2.22 Evaluating offset errors in terms of the equivalent voltages connected directly to the input terminals of the opamp. Thus Ib applies a voltage IbR source to the inverting input terminal and Ib applies a voltage IbRsource to the noninverting terminal. R source and Rsource represent the effective source resistance connected at the inverting and noninverting input terminals respectively. They represent the parallel combinations of all resistive paths to ground, including in the case of Rsource the path through any feedback resistor and the opamp output resistance to ground. Since Vio is directly applied to the input terminal, we may represent the total equivalent input offset voltage as eos ±Vio IbR source Ib Rsource
(2.27)
Drift in the total equivalent input offset voltage is obtained by substituting values of the drift coefficients of Ib and Vio.
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Graphs showing the dependence of eos drift on source resistance are given in some opamp data sheets. eos appears at the output multiplied by the ‘noise gain’ 1/; the resultant error may be referred to any signal input by simply dividing by the signal gain associated with that input. A numerical example should serve to clarify the evaluation of offset error. An opamp with Ib 100 nA, Iio 10 nA and Vio 1 mV is to be used in the inverting summing circuit shown in Figure 2.23. Find the minimum signals that can be amplified at the two input signal points with less than 1 per cent error due to offset.
Figure 2.23 Circuit for example of offset error evaluation
In the circuit of Figure 2.23, the noninverting input terminal is connected directly to earth, making Rsource zero. The effective source resistance through which bias current must flow to the inverting input terminal is Rsource R1 // R2 // Rf 8.3 k According to equation 2.27 eos 103 107 8.3 103 (worst case) 1.83 mV In this circuit Rf 1 1 12 R1 // R2 The output offset error is thus eos/ 22 mV. Referring this error to the e1 input the equivalent input error is 22/10 2.2 mV. Referring the output error to the e2 input the equivalent input error is 22/1 22 mV. The smallest input voltage for less than 1 per cent error is thus 220 mV at the e1 input, or 2.2 V at the e2 input. The input offset error due to bias current can be reduced, by connecting a resistor equal in magnitude to R source between the noninverting input and earth. This makes
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eos ±Vio IioRsource Accuracy is still relatively low, but can be improved if the initial offset is balanced out by using one of the offset balancing methods discussed in Section 9.6. An evaluation of subsequent offset error would then require knowledge of the temperature coefficient of Ib and Vio, and an estimate of the possible ambient temperature variations (T). Values Vo
Vio I T and Ib b T T T
should then be substituted in equation 2.27 in order to find the equivalent input error due to temperature drift.
An ideal differential opamp responds only to the difference in the voltages applied to its input terminals and produces no output for a common mode input voltage. In practical opamps, common mode input voltages are not entirely subtracted at the output due to slightly different gains between the inverting and noninverting inputs. The gain of an opamp for common mode input voltage is known as the common mode response. The ratio of the gain with the signal applied differentially to the common mode response is called the common mode rejection ratio, CMRR. It is often expressed in decibels (dB) by taking 20 times logarithm (base 10) of the ratio. Common mode rejection presents no problem for opamps used in the inverting configuration. This is because, with one input earthed, the input common mode voltage ecm must be zero. In noninverting circuits, feedback causes the voltage at the inverting input to follow that at the noninverting input. The input common mode voltage thus varies directly with the input signal. With finite CMRR an output signal is produced in response to this common mode input signal. Thus an error is introduced which affects the overall circuit accuracy. The common mode error is conveniently represented in terms of equivalent input common mode error voltage, ecm, where this is the common mode output divided by the differential gain. If the opamp is considered to have ecm applied to its noninverting input terminal, along with the input signal, it may then be treated as though it completely rejected the actual input common mode signal ecm. The relationship between input common mode error voltage and input common mode voltage is readily obtained as 1 ecm ecm CMRR
(2.28)
For example, consider an opamp with CMRR 1000 (60 dB) used in the noninverting configuration with an input signal of 1 V. The input common mode voltage ecm would also be 1 V. The input common mode error voltage is seen to be 1 mV and this represents a 0.1 per cent measuring error. The opamp is illustrated in Figure 2.24. It is not always possible to compensate for common mode errors. This is because the CMRR for some opamps shows a dependence on the magnitude
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CMRR
1+
1V
Figure 2.24 Representation of common mode error of the input common mode signal. Also, the common mode error voltage is a nonlinear function of common mode voltage and there is also an added complication of temperature dependence. Since linearity of common mode error voltage with common mode voltage is really more important than the actual value of the CMRR, a graph illustrating this relationship is valuable if an opamp is to be used in an application which is critically dependent on commonmode performance. Figure 2.25 illustrates an example.
CMRR
nonlinearly with ecm
Figure 2.25 Common mode error voltage as a function of common mode input voltage Specified values of CMRR where nonlinearities exist are usually average values, assuming a measurement of ecm at the end points corresponding to the maximum common mode voltage Ecm. It is important to note that published common mode specifications generally apply to DC input signals; CMRR is usually found to decrease at the higher frequencies.
2.11 Noise in opamp circuits
The output of an opamp is always found to contain random signals that are unrelated to the input signals. These unwanted signals are called noise. Errors such as drift error can, theoretically at least, be reduced to negligible proportions (by, say, using a temperaturecontrolled environment), but there always
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remains a noise error that limits the attainable accuracy and resolution. Noise should be taken into account if the circuit being designed must process lowlevel signals with high accuracy. There are two basically different types of noise in a circuit. Interference noise is picked up from outside the circuit. Inherent noise arises within the circuit itself. Sources of interference noise are many and varied. They include electromagnetic or electrostatic pickup from power sources at mains frequency, broadcast radio, electrical arcing at switch contacts and signals radiated from digital electronic circuits. Fortunately the circuit designer can usually minimize interference noise by suitable shielding and guarding and the elimination of earth loops (see Section 9.4) and by proper attention to mechanical design. Inherent noise is a function of a particular opamp and the circuit in which it is used. The only way in which the designer can influence inherent noise is through his choice of opamp and circuit components. The noise in an opamp can vary by several orders of magnitude.
2.11.1 Characterization of random noise sources The total noise that is inherent in an opamp circuit (or any circuit for that matter) can be thought of as a combination of the effects of several, separate, noise sources. These inherent noise sources are essentially random signals. They give an electrical signal whose waveform has no defined shape, amplitude or frequency. They may be thought of as a superposition of signals at all possible frequencies, with amplitude and phase varying in a completely random fashion. Root mean square (RMS) value of a noise source It is a characteristic of most forms of random noise source that averaged over a sufficiently long time interval their RMS value in a specified bandwidth remains constant. The RMS value in a specified bandwidth is thus a useful and meaningful way of characterizing a random noise source. The general defining equation is NRMS
1 T
T
n2i dt
(2.29)
0
where ni is the instantaneous noise amplitude (current or voltage), and NRMS is the RMS value of the noise source. In order to be meaningful, the RMS value of a noise source must have the bandwidth clearly defined. The wider the bandwidth: the greater is the RMS value of the noise. Combining noise sources The combined effect of several random noise sources is found by root sum of the square addition of the RMS values of the separate noise sources.
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Thus, if E1, E2, E3 are the RMS voltage values of three separate voltage noise generators their combined effect when connected in series is equivalent to a single noise voltage generator of RMS value E √E12 E22 E32
(2.30)
2.11.2 Peaktopeak noise In some applications it is peaktopeak noise which really sets the limit to a system performance. Peaktopeak noise is the difference between the largest positive and negative peak excursions to be expected during some arbitrary time interval. Random noise is, for all practical purposes, Gaussian in amplitude distribution; the highest noise amplitudes having the smallest (yet not zero) probabilities of occurring. Peaktopeak noise is thus difficult to measure repeatedly, but a useful rule of thumb for converting from an RMS noise value to a peaktopeak value is to multiply the RMS value by a factor of 6. The amplitude obtained is exceeded less than 0.25 per cent of the time by a random noise signal of the given RMS amplitude.
2.11.3 Noise density spectrum The noise generated by any random noise source exists in all parts of the frequency spectrum. The amount of noise contributed by a source varies with the range of frequencies over which the observation is made: NRMS(f1 – f2)
f2
n2 d f
(2.31)
f1
A noise density spectrum shows the way in which the noise produced by a given source is distributed over the frequency spectrum. Noise density n is shown as a function of frequency, usually on log–log axes. Examples of noise spectra are given in Figures 2.26, 2.28 and 2.29. In the spectral regions of interest in opamp applications, the noise sources encountered often have spectral distribution belonging to one of two types: in one, n is constant as a function of frequency; and in the other, n varies inversely with the square root of frequency.
2.11.4 White noise Noise for which n is constant with change in frequency is called white noise. The noise from a white noise source is distributed uniformly throughout the frequency spectrum. Thermal agitation of electrons in a resistor causes random voltages to appear across it. The spectrum of this noise voltage is characterized by a noise density that is constant as a function of frequency. Resistance noise
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Figure 2.26 Noise density spectrum for opamp generated noise (Johnson noise) is thus an example of white noise. The noise voltage associated with a resistor has a noise density: Resistance noise e √(4kTR) V per √Hz
(2.32)
where: k Boltzmann’s constant 1.37 1023 J/K, T the temperature in K and R the resistor value in . The RMS noise voltage generated by a resistor R, in the range of frequencies f1 to f2, is: Resistance noise eRMS(f1 – f2) √4kTR (f1 – f2) volt RMS
(2.33)
2.11.5 1/f or ‘pink’ noise Noise, which has a density that varies inversely with the square root of frequency, is referred to as 1/f noise. This is sometimes called ‘pink’ noise. The noise density for a pink noise source is determined by an equation of the form Pink noise n K
1 f
(2.34)
where K is the value of n at f 1 Hz. A graph of n against frequency for a pink noise source when shown as a log–log plot is a straight line of slope 10 dB/decade. A graph of n2 against frequency gives a straight line of slope 20 dB/decade. The contribution which a pink noise source makes to the RMS value of the noise in a frequency range f1 to f2 may be found by substituting equation 2.34 into the general equation 2.31. Thus:
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NRMS(f1 – f2) K
dff k ln ff f2 f1
2
(2.35)
1
Note that the RMS noise contributed by a pink noise source in a particular bandwidth depends upon the ratio of the frequencies defining that bandwidth. Every frequency decade of noise from a pink noise source has the same RMS value as every other decade.
2.11.6 Evaluation of RMS noise from a noise density spectrum The contribution that a particular noise source makes to the RMS noise in any specified bandwidth can, in principle, be found by evaluating the integral in equation 2.31. Equations 2.33 and 2.35 are the results of such evaluations for the particular cases of a white noise source and a pink noise source. Note that in order to evaluate the integral the equation defining the noise density as a function of frequency must of course be known. In the spectral regions of interest, the noise generators used to represent the effect of internally generated opamp noise often exhibit a noise density spectrum of the form shown in Figure 2.26. A spectrum of this kind can be thought of as consisting of two components; a white noise component, which is the predominant noise component at high frequencies, and a 1/f component which predominates at low frequencies. The RMS value of the noise contributed by the source in any bandwidth can be found by a root sum of the squares addition of the RMS contributions of the two separate components in that bandwidth.
2.11.7 Opamp noise specifications The noise present at the output of an opamp is a combination of the amplified noise present at its input and noise generated internally inside the opamp. Noise produced internally by an opamp is conveniently modelled as shown in Figure 2.27, by a noiseless opamp with a noise voltage and a noise current generator at its input terminal.
Noiseless opamp
Figure 2.27 Opamp model for internally generated noise
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Equivalent noise generators connected to the opamp’s input terminals could be used to represent noise generated by resistors at the input. The several input contributions to the noise can be combined as a single resultant inputreferred noise source and in closedloop opamp applications this total inputreferred noise appears at the output multiplied by the closedloop noise gain 1/. The technique for noise evaluation, just described, is similar to the technique for evaluating offset and drift errors, previously described in Section 2.9.3. The main difference between a drift error evaluation and the evaluation of noise errors is the dependence of noise on bandwidth. In making a noise assessment of an opamp circuit, the designer must use noise data from the opamp data sheet. Opamp noise data will be found presented in both graphical and numerical form. An example of graphical data is given in Figure 2.28, where the frequency dependent nature of the noise can be seen. Numerical noise data is usually given in terms of voltage noise and current noise, as modelled in Figure 2.27. Some manufacturers specify typical peaktopeak input voltage and current noise in a low frequency band (say 0.01 to 1 Hz). A peaktopeak specification of this kind is particularly useful in assessing accuracy limits (as limited by noise) in applications in which the signals of interest are essentially DC, or very slowly varying quantities. Wide bandwidth noise will of course be present in the opamp output but it can be removed by following the opamp with a suitable lowpass filter. RMS values of noise can be used as a means of estimating peaktopeak values. The rule of thumb multiplication factor of 6, mentioned previously, is used.
2.11.8 Evaluating noise errors using noise specifications The problem facing the circuit designer is to assess accuracy and resolution limits as determined by noise. Clearly if the noise level at the output is comparable to the signal level, the signal is obscured by the noise. In wide band applications signaltonoise ratio (SNR) is a useful figure of merit in describing how well the signal ‘stands out’ from the noise. The signaltonoise ratio at the output is defined as SNR signal power out/noise power out The ratio is sometimes expressed in decibels (dB) by the relationship SNR(dB) 10 log(Ps/Pn)
(2.36)
In DC and low frequency applications, accuracy limits determined by noise can be related to peaktopeak noise. Noise error is expressed as a percentage, from the relationship: peaktopeak value of output noise Noise error peaktopeak value of output signal 100%
(2.37)
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Figure 2.28 Noise spectral density for a typical opamp An estimate of the amount of noise to be expected in a given circuit is made by using the noise data for the opamp used. Rigorous noise evaluations are time consuming and can be of dubious practical value if they are based upon ‘typical’ noise data. In many applications the effect of a single noise source can be dominant, and the ability to identify the most significant noise contributions allows a rapid orderofmagnitude noise assessment. As a starting point in any noise evaluation, the signal gain and the noise gain in the circuit should be found. Bode plots giving their frequency dependence help to show up the spectral regions where significant noise contributions are to be expected. An evaluation of the noise performance of
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Figure 2.29 Noise evaluation example 1 an opamp used in a basic resistive feedback configuration is taken as a first example, Figure 2.29. Input noise sources appear at the opamp output multiplied by the noise gain; in this example the noise gain is 100, its 3 dB bandwidth limit is 104 Hz and it rolls off at 20 dB/decade beyond this frequency. Using equivalent input noise generators Noise voltage and noise current can be used to find the total noise. In order to calculate the total noise, both noise sources need to be described in the same form. Noise voltage is normally used. To convert the noise current (In) into voltage form it is multiplied by the resistance presented to the opamp’s inputs.
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Thus we have en1 IinRsource en2 IinRsource Simplifying into one noise generator, where Rs is the effective resistance between the opamp’s two inputs (given by SS √(R1//R2)2 R32 in Figure 2.29), we have ein IinRs The total intrinsic noise is √[en2 (InRs)2]. The voltage and current generators have equal contribution to the intrinsic noise when en InRs. This occurs when Rs Rn en/In, and Rn is known as the noise resistance. If the resistance presented to the opamp’s inputs is much lower than en/In, the intrinsic noise can be considered due to the voltage generator alone. Conversely, if the resistance is much higher than en/In, the intrinsic noise is due to the current generator alone. Lowering an AC opamp’s noise figure The noise figure of the opamp is described as the signaltonoise ratio at the output divided by the signaltonoise ratio at the input. This is often measured as a voltage, but expressed in decibels (dB) by taking 20 log(voltage ratio). In other words, it is the amount of noise added to the signal by the opamp. If the resistance presented to the opamp’s input is lower than the noise resistance, the opamp’s voltage noise will dominate. The noise power is this voltage squared, multiplied by the resistance presented to the input. One way to minimize the noise contribution of an opamp is to transformer couple the input signal with a stepup transformer (1:N). When a stepup transformer is used, the signal voltage is multiplied by the turnsratio (N). The effective impedance seen by the opamp input is the source resistance multiplied by N squared. Assume that the opamp’s input impedance must match the source impedance. First, we choose a value of N such that N 2 2Rn, for the signal impedance given. Second we terminate the secondary of the transformer with a load resistor equal to 2Rn. The opamp’s inputs now see impedance Rn, and both Vn and In contribute to the total noise. The equivalent voltage noise is now (√2)en, or 3 dB above en. Suppose Rn 3 k and the signal impedance is 600 . We choose a transformer ratio of 1:3.16. The 600 primary impedance is transformed up to 6 k at the secondary. A load of 6 k is then applied across the secondary winding. The input voltage is increased by 10 dB (20 times log(3.16)). Since the impedance at the opamp’s input equals Rn, the total input noise is only increased by 3 dB. Therefore this circuit has raised the signaltonoise ratio by 7 dB, compared to a circuit with a 600 resistor across its input. This is shown in Figure 2.30.
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Rn = 3k
1 : 3.16 600R Input
6k
Output
+ _ R2 R1
Voltage gain = 3.16 + (1+ R2/R1)
Figure 2.30 Transformer coupled opamp input In some circuits, impedance matching is not required. This is usually where the source and load are physically close. If there is a transmission line between source and load, matching is often necessary. Unmatched transmission lines suffer from reflections and crosstalk from other signal carrying circuits. The important notion of noise resistance can lead to a misunderstanding. The resistance of a source should not be artificially raised to be equal to the noise resistance. This will increase thermal noise due to the extra resistance in series with the signal path. Transformer coupling, to increase the effective source resistance, works because the signal voltage is also raised in the process. The use of a transformer gives additional benefits. Transformer coupling, using an earthed screen between primary and secondary windings, increases the rejection of common mode signals. Transformers are designed to cover a specified range of frequencies and tend to reduce the amplitude of signals outside this range; hence they act as first order bandpass filters.
Exercises
2.1 An opamp is to be used in the inverting feedback configuration with a closed loop signal gain of 100 and an input resistance of 10 k. (a) Assuming ideal amplifier performance what values of input and feedback resistor should be used? (b) If the opamp is assumed ideal except for a finite loop gain of 104, by how much will the signal gain differ from 100? (c) If the openloop gain of the amplifier changes by 5 per cent what effect will this have on the closedloop signal gain? 2.2 The amplifier used in the circuit of Figure 2.5 has an openloop gain 5 104 and differential input resistance 100 k, resistor R1 1 k, R2 3.9 k. Find the closedloop gain and the effective input resistance of the circuit. Assume that the common mode input impedance of the amplifier is infinite and that its output resistance is negligible. 2.3 Write expressions for the feedback fraction and the closedloop gain 1/ for the circuits given in Figures 1.3, 1.4(b), 1.6, 1.7 and 1.8. 2.4 Express the following voltage ratios in decibels to the nearest whole dB. (a) 1, (b) 2, (c) 3, (d) 10, (e) 100, (f ) 1000, (g) 106.
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2.5 Without using log tables, using only the results of Exercise 2.4, calculate the dB equivalents of the following voltage ratios to the nearest whole dB. (a) 6, (b) 15, (c) 3.33, (d) 333, (e) 9, (f) 0.01, (g) 0.05, (h) √2, (i) 1/√2. (Hint: 3.33 10/3. Thus (3.33 expressed in dB) (10 expressed in dB) (3 expressed in dB).) 2.6 An opamp has an openloop frequency response that exhibits a 20 dB/decade rolloff down to unity gain. Its open loop gain at zero frequency is 100 dB and its unitygain frequency is 1 MHz. Sketch the openloop frequency response on a dB/log f plot: (a) The amplifier is connected as a noninverting feedback amplifier (a follower) with closedloop gain (i) 2, (ii) 10, (iii) 50. Find the smallsignal closedloop bandwidth in each case and sketch the appropriate Bode plots. (b) The amplifier is connected as an inverting adder, as in Figure 1.4(b), so as to form the weighted sum of three separate signals. Input resistors R1 27 k, R2 39 k, R3 56 k, and a feedback resistor Rf 120 k, are used. Find (i) the ideal performance equation, (ii) the value of 1/ for the circuit, (iii) the smallsignal closedloop bandwidth, (iv) by how much the ideal performance equation is in error at a frequency 20 kHz (see Section 2.4). 2.7 An opamp has a slew rate of 0.5 V/ s. What is the maximum frequency for which the amplifier will give an undistorted sinusoidal output signal of (a) 20 V peaktopeak; (b) 10 V peaktopeak? (see Section 2.8). 2.8 An opamp employing the frequency compensating technique discussed in Section 2.6 has a frequency compensating capacitor of value 10 pF connected to it. When it is used as a unitygain follower, it has a closedloop frequency response that exhibits 5 dB of gain peaking. What damping factor and overshoot do you expect in the smallsignal step response of the follower? What minimum value of frequency compensating capacitor would be required for no gain peaking, and what overshoot would result in the smallsignal step response if this value of capacitor were connected? 2.9 The openloop gain of an opamp is 100 dB at DC and its openloop frequency response exhibits two breaks at frequencies fc1 100 Hz, fc2 4 MHz. The amplifier is connected as a unity gain follower. At what frequency is the magnitude of the loop gain unity? What is the phase margin in the circuit? By how much does the closedloop gain peak and at what frequency does the gain peak occur? Estimate the settling time to 0.1 per cent if a small input step signal is applied. Find the minimum closedloop gain for which the amplifier will exhibit (a) no closedloop gain peaking; (b) a critically damped response with no overshoot in the transient response. Find the closedloop 3 dB bandwidth for each of these values of closedloop gain (see Section 2.7 and Appendix A2).
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2.10 An opamp has the following offset and temperature drift specifications: Vio 2 mV; Vio/T 10 V/°C; IB 500 nA; IB/T 1 nA/°C; Iio 50 nA; Iio/T 0.1 nA/°C. The amplifier is connected as a simple inverter with R1 10 k, Rf 1 M, and is supplied by a signal source of negligible resistance. Find: (a) the output offset voltage; (b) the change in output offset voltage to be expected from a temperature change of 10°C; (c) assuming initial offset balanced, the smallest input signal that can be amplified with less than 1 per cent error, due to a 10°C temperature change; (d) the value of a resistor Rc that should be connected between the noninverting input terminal and earth to reduce the offset error due to amplifier bias current. Repeat parts (a), (b) and (c), assuming that the resistor Rc is connected in the circuit. In all cases assume worst case errors (see Section 2.9.3). 2.11 An opamp with the offset and temperature drift specifications given in Exercise 2.10 is to be used as a follower with a feedback resistor of 10 k and a resistor of 1 k connected between the inverting input terminal and earth. The circuit is supplied by a signal source of internal resistance 100 k. Find: (a) the output offset error with no offset balance; (b) the smallest input signal that can be amplified with no more than 1 per cent error if initial offsets are balanced and the temperature changes by 10°C (see Section 2.9.1). 2.12 A differential input opamp, assumed ideal except for finite openloop gain and finite CMRR, has an open loop gain of 5 104. When the opamp inputs are connected together, and a signal of 1 V with respect to earth is applied to them, the output voltage of the amplifier is found to be 5 V. Find the CMRR of the amplifier and the measurement error due to common mode signals (expressed as a percentage), when the amplifier is used as a noninverting feedback amplifier. 2.13 A random noise voltage source has a noise density function which varies inversely with frequency; the RMS value of the noise voltage produced by the source is 2 V in the frequency range 20 Hz to 100 Hz. Find the RMS noise voltage produced by the source in the frequency range: (a) 1 Hz to 10 Hz, (b) 10 Hz to 100 Hz, (c) 1 Hz to 1 kHz (use equation 2.35). 2.14 The input connected noise voltage and noise current generators that are used to represent the noise generated by an opamp have noise density spectra consisting of white noise and 1/f components. The noise voltage generator has a white noise component with density 20 nV/√Hz and a
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1/f corner frequency of 50 Hz. The current generator has a white noise component with density 0.3 pA/√Hz and a 1/f corner frequency of 1 kHz. Sketch the noise density spectra. Find: (a) the RMS value of the noise voltage generator; (b) the RMS value of the noise current generator, in the frequency ranges (i) 0.1 Hz–10 Hz, (ii) 1 Hz–100 Hz, (iii) 1 Hz–1 kHz, (iv) 1 Hz–10 kHz; (c) the RMS value of the total input referred noise voltage in the above frequency ranges for source resistance 1 k, 10 k, and 100 k.
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3 Analogue integrated circuit technology
+ _ R2
Vin Vfb
Io
Io=Vout/(R1+R2)
Vout
R1
Vin ~ Vfb = Vout R1 / (R1 + R2)
Figure 3.1 Voltage feedback amplifier
Iinv V= I x R1
R Vo 1 2 VIN R1
1 1
1 LG
AOL AOL R2 1 R1 Current feedback refers to any closedloop circuit that uses an error signal in the form of a current (see Figure 3.2). Unlike voltage feedback opamps, current feedback devices have a low impedance inverting input. The low impedance allows current to flow into and out of the inverting input. Any current flow at this input is an error current, and the opamp produces an output voltage in proportion to its magnitude. Current feedback is used to maintain zero error current at the inverting input. The noninverting input is high impedance, like that of a voltage feedback opamp. The heart of a current feedback opamp is a transimpedance amplifier. The transimpedance amplifier produces a voltage output from a current input. Here loop gain (LG) is given by
+ _ Vin
This chapter describes the technology used within analogue integrated circuits, concentrating on opamps. It will also describe the differences between voltage feedback and current feedback. The technology is determined by the type of transistor used in the integrated circuit (IC). The types include bipolar, bipolar with JFET inputs, LinCMOS (linear CMOS) and BiCMOS (incorporating bipolar and CMOS transistors). The majority of opamps are designed to use voltage feedback. However, current feedback devices are now employed in radio frequency and video signal processing because they have a very wide bandwidth capability. It may be useful to define (i) voltage feedback, and (ii) current feedback. Voltage feedback refers to a closedloop configuration in which the error signal is in the form of a voltage (see Figure 3.1). Traditional opamps use voltage feedback and produce an output voltage in response to a difference in voltage at their inputs. In other words, their inputs respond to voltage changes. The ideal voltage feedback opamp has high impedance inputs and zero input current. Voltage feedback is used to maintain zero differential input voltage. The transfer function of a noninverting voltage feedback amplifier is given by:
R2
I = Io  Iinv
Io
Vout
R1
At balance, Iinv ~ 0, hence I = Io Vin ~ Io R1 = Vout R1 / (R1 + R2)
Figure 3.2 Current feedback amplifier
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As the function implies, the openloop ‘gain’, Vo/Iin, is expressed in ohms. We will consider this impedance in its separate resistive (Rm) and capacitive (CC) forms, or as a complex impedance Z(s). Hence a current feedback opamp is sometimes called a transimpedance amplifier. The transfer function of a noninverting current feedback amplifier is given by:
Vo R 1 2 VIN R1
1 1
1 LG
In this case loop gain (LG) is given by LG
Z(s) R2
The closedloop gain now depends on just R2 and the opamp’s transimpedance Z(s).
3.1 Voltage feedback opamps
Opamp integrated circuits employing bipolar transistors have been used since 1965. These opamps were a great improvement on discrete ‘operational amplifiers’ that were built using individual transistors, resistors and capacitors. They were smaller, low cost and simple to use. Field effect transistors were later used in some opamps to improve certain aspects of bipolar opamp performance. Devices with JFET input transistors, but otherwise using bipolar transistors throughout, were developed in the late 1960s. The advantage of the JFET input opamp was reduced input bias current requirement. JFET input opamps were called ‘BiFET’ opamps by Texas Instruments; this name is very descriptive since it employs bipolar and FET transistors. Opamps that use CMOS transistors throughout have been used more recently to allow very low power operation. Further development has produced BiCMOS opamps, employing both bipolar transistors and complementary MOSFET transistors. 3.1.1 Bipolar opamps The problem with the original (1965) opamp designs was that the input impedance was much lower than the ideal (about 200 k). Also the input bias current and offset voltages were significant. Continual development work by several semiconductor manufacturers has enabled the performance of bipolar opamps to improve steadily. Bipolar opamps have a typical input impedance of about 10 M, but negative feedback can increase this to 1 G or more. The greater problem is that input bias currents are in the order of 10 nA, and the resulting noise current is in the order of 0.3 pA/√Hz. These levels of bias and noise current make bipolar opamps unsuitable for use with high impedance sensors. Bipolar opamps use fast npn and pnp transistors. Typical input and output circuits were described in Chapter 2 (Figures 2.1 and 2.3). These allow the device to have a gain–bandwidth product of 10 MHz or more. Good matching between the input transistors not only reduces the input offset voltage, but
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also reduces drift with temperature and with time. Opamps with a bipolar input stage have the greatest longterm stability of all existing technologies. One reason is that collector currents flow vertically through the semiconductor, and hence are not subject to lateral stress and strain due to temperature. The noise voltage in a bipolar transistor is due to the emitter resistance, and this is far lower than the equivalent resistance in JFETs or MOSFETs. Hence the noise voltage is lower in a bipolar input stage, compared with a FET input stage. Typical noise voltage is 15 nV/√Hz, although low noise types have a noise voltage below 5 nV/√Hz.
3.1.2 Complementary bipolar (Excalibur) technology There are thousands of different types of integrated circuit opamps available commercially, and the number is increasing almost daily. The many manufacturers of these different types are trying to produce the best devices by giving them improved DC precision, faster AC performance and lower power consumption. One difficulty in improving the performance of opamps is the relative slow response of the pnp transistor compared with that of the npn. The reason for this is the low mobility of the majority carrier ‘holes’ in the pnp transistor, compared with that of the electrons in the npn transistor. Many opamp designs use pnp transistors, particularly in input stages that use differential pair transistors; they are also used in emitter follower outputs. However, the pnp transistor has a typical fT of only 5 MHz compared with 150 MHz for the npn transistor. One method of increasing the speed of slow complementary bipolar circuits is to increase the speed of the npn element, so the overall speed increases. This is the approach of several semiconductor manufacturers. Conventionally, a vertical structure in the silicon die is used to create transistors. An npn transistor will have a ptype substrate and an ntype epitaxial layer. In theory, faster pnp transistors can be achieved by simply reversing this design, with a substrate of ntype silicon. Although this method successfully increases the pnp transistor speed, it reduces the speed of the complementary npn fabricated in the same IC. In contrast to this, Texas Instruments has developed a manufacturing process for a fast vertical pnp device structure that retains the speed of the npn devices. Texas Instruments call this their Excalibur process and it uses a deeply submerged nregion as an ‘artificial substrate’ in which a buried pregion becomes the collector. The fast pnp Excalibur transistor can be integrated directly into the signal path without fear of limiting the bandwidth or slew rate. This often has the added benefit of requiring less supply current than its predecessors. An example of the Excalibur range of opamp is the TLE2021, which is a low power, precision opamp. The TLE2021 achieves a unitygain bandwidth in excess of 2 MHz and a slew rate of 0.9 V/s. The supply current is less than 200 A with an input voltage offset of less than 100 V. A common problem with many opamps is that they suffer from ‘phase inversion’. This happens if the input swings close to the power rail potential, causing the output to change state and swing to the opposite rail. Many
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of the older bipolar and BiFET opamps are known to have this problem. Many newer products, such as the TLE2021 family, have been designed to avoid this.
3.1.3 ‘Chopper’ stabilization The TLC265X family of CMOS technology opamps offers enhanced DC performance using a technique known as chopper stabilization. The chopper opamp is designed continuously to undertake selfcalibration to provide an ultra low offset voltage, which is extremely time and temperature stable. At the same time, the CMRR is increased and the 1/f noise content is reduced. Figure 3.3 shows a typical chopper stabilized opamp.
Figure 3.3 Chopper stabilized opamp Basically, the enhanced performance of a chopper stabilized opamp is achieved by using two opamps. A nulling opamp and a main opamp are used together with an oscillator, switches and two external (or internal) capacitors to create a system that behaves as a single opamp. With this approach, the TLC2652 opamp achieves a submicrovolt input offset voltage and a submicrovolt input noise voltage. Offset variations with temperature are in the nV/°C range. The onchip control logic produces two dominant clock phases: a nulling phase and an amplifying phase. During the nulling phase, switch ‘A’ is closed, shorting the nulling opamp inputs together. This allows the nulling opamp to reduce its own input offset voltage, by feeding its output signal back to an inverting input node. Simultaneously, the external capacitor, CXA, stores the nulling potential, to allow the offset voltage of the opamp to remain nulled during the amplifying phase. During the amplifying phase, switch ‘B’ is closed. This connects the output of the nulling opamp to the noninverting input of the main opamp. In this configuration, the input offset voltage of the main opamp is nulled. Also, the external capacitor, CXB, stores the nulling potential, to allow the offset of the main opamp to remain nulled during the next phase.
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This continuous chopping process allows offset voltage nulling during variations in time and temperature. The nulling process works over both the common mode input voltage range and the power supply voltage range. Additionally, because the low frequency signal path is through both the nulling and main opamps, an extremely high gain is obtained. The level of low frequency noise output from the chopper opamp depends upon the magnitude of component noise prior to chopping. It also depends upon the capability of the circuit to reduce this noise while chopping. Increasing the chopping frequency reduces the low frequency noise. Limiting the input signal frequencies to less than half the chopping frequency reduces the effects of intermodulation and aliasing.
3.1.4 JFET input opamps Junction field effect transistors (JFETs) were introduced into opamp input stages in an attempt to increase the input impedance and reduce the bias current. The intermediate and output stages of the opamp continued to use bipolar transistors, as shown in Figure 3.4.
In 1
In 2 Cc
Out
Figure 3.4 JFET input opamp circuit Opamps with JFET inputs have very high input impedance, typically 1 T. Their input bias current is typically 50 pA and their noise current is about 10 fA/√Hz. Noise voltage is higher in JFET input opamps than in bipolar devices, due to the high channel resistance. The noise voltage is typically 20 nV/√Hz. Input offset voltages in JFET input opamps (typically 500 V) are about ten times that for bipolar input opamps. The stability of a JFET input opamp is also far worse than for a bipolar input device. Current flow through a lateral JFET channel is subject to stress and strain due to temperature, which results in changes in the channel current. Special circuits that use bipolar transistors to reduce input offset voltage drift are used in the ‘Texas Instruments’ Excalibur process. The JFET at the input does not allow as much gain as in a bipolar stage. Because of this, greater slew rates can be achieved than for a bipolar input opamp having the same gainbandwidth product. A fast slew rate makes
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JFET input opamps suitable for use in rectifier circuits, peak detector circuits, pulse amplifying circuits and sample and hold circuits.
3.1.5 CMOS opamps Digital electronics has employed CMOS transistors for many years, in order to reduce the size and power consumption of circuits. Power consumption has been reduced by the combination of low voltage and low quiescent (steady state) current requirements. Now analogue opamps use CMOS for similar reasons, as shown in Figure 3.5.
In 1
In 2
Bias Intermediate stages
Output
Active Load
Figure 3.5 CMOS opamp circuit Opamps are available that draw just 1 A quiescent current from their supply rails. Devices that operate from supply voltages as low as 1.4 V are also available. Most CMOS opamps are unable to operate with supply voltages greater than 16 V and many are limited to about 6 V operation. As a result of using pchannel MOSFETs on their input, CMOS opamps can operate correctly with input voltages down to the negative supply rail. This makes them suitable for use in single supply circuits where the input voltage is referenced to the negative rail. The MOSFET input provides high input impedance, with low offset and bias currents. The input bias current is typically about 100 fA. However, like the JFET input, this current doubles for every 10°C rise in temperature. The CMOS opamp is therefore susceptible to drift with temperature. Offset voltages are typically 1 mV, although some opamps are designed for offset voltages as low as 200 V. This is better than many JFET input opamps, but not as good as can be achieved with bipolar devices. Chopper stabilized CMOS opamps achieve high DC precision, with maximum offset voltage in the order of 1 V. The offset voltage stability is generally better in CMOS opamps than in JFET input devices. Unfortunately, CMOS opamps suffer from high noise voltage. Noise voltage is typically 30 nV/√Hz, although some devices have been designed for low noise and produce a noise voltage of about 10 nV/√Hz. This level of noise is lower than that of JFET input opamps, and lower than some bipolar types.
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The single supply, low voltage and low quiescent current requirements make CMOS opamps ideal for portable equipment. The high input impedance and low bias current make them suitable for interfacing high impedance transducers. To prevent damage due to electrostatic discharge (ESD), care has to be taken with all electronic devices. Bipolar and JFET inputs will conduct when a high voltage is applied. If reverse biased, a pn junction will break down temporarily, like a zener diode. Provided that current flow is limited, no permanent damage occurs. The very high impedance of MOSFET input opamps makes them more susceptible to ESD damage. Overvoltage applied to an input will permanently damage a MOSFET gate by burning a hole in its surface.
3.1.6 BiCMOS opamps BiCMOS technology has been used in logic integrated circuits for a few years, but until the late 1990s there were few BiCMOS analogue devices. However, the move to BiCMOS has been encouraged by the need to use singlerail lowvoltage power supplies. Opamps are available that operate from a singlerail supply, typically between 2.7 V and 12 V, and draw very little current. They are therefore suitable for batteryoperated equipment. The input stage of a BiCMOS opamp is illustrated in Figure 3.6. The current source connected to the V supply limits the current into the circuit, and the bipolar transistors form an amplified current mirror. If the voltage at input IN1 is made negative to increase the current flow through the MOSFET Q1, then more current flows through the base of Q3. This current is amplified by Q3 and then used to drive the bases of Q4 and Q5. An increase in current through Q5 lowers the output voltage. Thus the gain of this stage is very high due to the amplified current mirror. Like CMOS opamps, the use of pchannel MOSFETs at the input allows the BiCMOS opamp to operate down to the negative supply rail. They are ideal for single supply operation where the input voltage is referenced to the negative supply rail. The MOSFET input gives very high input impedance and bias currents of 1 pA are typical. One advantage of BiCMOS is the ability to produce a good output bandwidth and slew rate, whilst drawing little current from the supply. One device, the TS951, is intended for use in mobile phones. This opamp draws 0.9 mA from the supply and delivers a gainbandwidth product of 3 MHz. Another opamp, the LMV321, requires just 0.1 mA to deliver a gainbandwidth product of 1 MHz.
3.2.1 DC considerations Table 3.1 shows typical DC performance figures and highlight some of the features and benefits for the three basic types of opamp technology: bipolar, BiFET and CMOS.
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Table 3.1
DC comparison of voltage feedback opamps
DC parameter
Bipolar
BiFET
CMOS/BiCMOS
Input offset voltage Input offset voltage drift Input bias current Input bias current drift
10 V–7 mV 0.1–10 V/°C
500 V–15 mV 5–40 V/°C
200 V–10 mV 1–10 V/°C
100–50 000 pA Fairly stable with temperature change
1–100 pA Doubles for every 10°C increase
0.1–10 pA Doubles for every 10°C increase
Bipolar features Very low offset and drift; allow low level signal conditioning. Stable bias current; remains low at high temperature. High voltage gain; ensures accurate amplification. Lowest voltage noise; wide dynamic range. BiFET features Very low input bias and noise current; matches high impedance circuits. Good AC performance; useful for combined AC and DC applications. CMOS features Very low input bias and noise current; matches high impedance circuits. Single supply operations; can be operated from battery or 5 V supply. ‘Chopper’ stabilizing techniques are used to overcome the large input offset drift prevalent in standard MOS devices; can be used to amplify very small signals and provide a wide dynamic range. BiCMOS features DC operation of BiCMOS is similar to that of CMOS. Very low input bias and noise current that matches high impedance circuits and the ability to operate from low voltage, single rail supplies. Comparing DC errors for the different types of opamp shows that the newer bipolar designs are better than the older LM741 and LM301 devices. The input offset and bias current have been greatly reduced, while the openloop gain has been increased dramatically. BiFET opamps normally have higher input offset voltage and drift, compared with bipolar devices. However, the input bias current of FET opamps is insignificant when compared with that of bipolar devices. The FET bias current doubles for every 10°C temperature increase. Note that some bipolar designs actually have lower bias currents at higher temperatures than FET input opamps. Silicon gate CMOS technologies such as LinCMOS have reduced the problem of unstable offsets in CMOS designs. The TLC2201, designed using LinCMOS, is an example of the new breed of CMOS devices. It offers extremely low and stable offsets while simultaneously featuring the high
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input impedance and low noise current found in the best of JFET devices. For high order DC precision, the chopper stabilized opamps, such as the TLC2652, provide the lowest input offset and drift. 3.2.2 AC considerations Opamps require both AC and DC accuracy. While input offset voltages and bias currents are relevant in DC applications, other parameters must be considered for AC circuits. The opamp is designed to perform an amplification function. Unfortunately, amplification of the signal is usually accompanied by a phase shift, which can lead to instability of the device. To prevent instability, a Miller compensation capacitor is used, but only at the expense of the slew rate and gain of the opamp. Ultimately this compensation capacitor defines the unitygain bandwidth. The AC performance of an opamp is determined by the process technology used in manufacture, or the design techniques employed. Wide bandwidth devices usually have high supply current requirements. Bipolar opamps offer good gain and bandwidths but their slew rate for a given bandwidth is slow. This is a limitation of the bipolar technology process (high transconductance, gm) and is not easily designed out. As discussed in Section 3.1.1, the use of pnp transistors in bipolar opamps provides a speed limitation. BiFET opamps are designed using a combination of bipolar and JFET structures. Pchannel JFETs (with much lower transconductance than have bipolar transistors) are used in the input stage. The remaining circuit is designed using bipolar transistors. This combination has produced opamps with significantly higher slew rates than purely bipolar designs. CMOS technologies such as LinCMOS have a similar performance to designs using BiFETs, but are of particular benefit for low power or single supply applications. BiCMOS techniques have many of the same qualities as CMOS, except that for a given supply current they have much higher dynamic response. The slew rate and gainbandwidth product of BiCMOS opamps is generally greater than a CMOS opamp that draws the same current. They are widely used in the audio amplifier circuits of mobile telephones. 3.2.3 Noise considerations An opamp’s input voltage noise is described in terms of nanovolts per root hertz (nV/√Hz). This level is higher at very low frequencies than across the majority of the opamp’s operating bandwidth. The break point where the noise level ‘flattens out’ is known as the 1/f corner frequency. Below the 1/f corner frequency, the noise level rises inversely proportional to frequency. In a bipolar opamp, the 1/f corner frequency can be as low as 100 Hz, but in FET input opamps this frequency can be much higher (several kHz). Bipolar devices offer the lowest voltage noise among those commercially available, typically 15 nV/√Hz, although some devices have much lower voltage noise levels (< 5 nV/√Hz). The voltage noise from a bipolar input stage, in the flat part of the band, is dominated by thermal noise from the basespread
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resistance and the emitter resistance. Unfortunately, the shot noise arising from the input bias current can be significant. Therefore, in order to reduce this current noise, bias current cancellation circuits are sometimes used. The input noise current of FET input opamps is caused by shot noise, due to the gate current. This is very low at temperatures around 25°C compared with the base current in bipolar inputs. Consequently, FET input opamps have negligible input current noise and provide a superior noise performance with high impedance sources. A FET input stage has higher voltage noise and higher 1/f corner frequency than a bipolar input stage. The gate current is negligible and the input current is reduced to leakage current by the input protection network. The noise sources of a MOSFET input device are similar to those of the junction FET. A common disadvantage of MOSFET input opamps (i.e. CMOS and BiCMOS opamps) is their relatively high voltage noise and high 1/f frequency. In contrast, some devices (e.g. the Texas Instruments LinCMOS opamp, TLC2201) offer current noise levels similar to the very best junction FET input opamps. They also have voltage noise levels comparable to many bipolar designs. The TLC2201 features low input offset voltages coupled with a very low drift with time and temperature change. Additionally, the device features operation from a single 5 V supply and railtorail output swing. In summary, bipolar input stages give the lowest voltage noise and lowest 1/f corner frequency and are well suited for interfacing with low impedance sources. JFET, CMOS and BiCMOS input stages have negligible input current noise, allowing them to be used with extremely high source impedances. Noise current is related to the input bias current and it will increase by V2 for every 10°C rise in temperature. 3.2.4 Power supply considerations Opamps are required to operate with many different supplies. Circuits may be battery powered and required to run off a single 1.5 V supply or they may have a 22 V or more supply in an instrumentation application. The available power affects the choice of opamp. Single supply opamps will normally need to operate from a low voltage supply, maybe as low as 1.5 V if used with battery powered equipment. They will also require an input common mode range down to the negative rail and an output that swings near to ground. These restrictions do not usually apply to dual supply opamps. An opamp with a common mode range down to the negative rail can easily be designed using a bipolar process. PNP input transistors ensure that the input can swing down to the negative rail, or below, without causing problems. A good output swing is not so easy to achieve. Many bipolar devices are optimized for dual supply operation, that is, capable of sinking and sourcing current. This therefore means that the output will not normally swing down to the negative rail. If a device is optimized for single supply operation, its output suffers from crossover distortion when it is operated with dual supplies. Bipolar devices suitable for both single and dual power supply operation are uncommon.
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BiFET opamps have been designed for dual supplies and are generally unsuitable for single supply operation. Their common mode input range reaches (and sometimes exceeds) the positive supply rail potential. The output will normally swing to within 2.5 V of each supply voltage. They operate from a wide range of supplies (3 V to 22 V) and are optimized for AC performance. CMOS devices (LinCMOS) and BiCMOS have been specifically designed for single supply operation. The supply voltage range is typically 2 V to 16 V. The input voltage range extends below the 0 V supply. The output voltage swing can approach the power rails for high impedance loads. Unlike bipolar designs, CMOS devices with push–pull outputs can also perform well with dual supplies. However, a limitation in some dual supply applications is the limited operating voltage.
3.3 Current feedback opamps
The disadvantage of voltage feedback opamps is that the gainbandwidth product is constant. Extending the bandwidth is at the expense of gain. Current feedback opamps have an entirely different gainbandwidth product relationship. In fact, the bandwidth is almost constant, irrespective of gain. The simplest model of a current feedback amplifier is shown in Figure 3.7. In this model, the input of a current feedback amplifier is a buffer, connected between the noninverting and inverting inputs. The noninverting input is connected to the buffer input and has high impedance. The inverting input is connected to the buffer output and has low impedance. Current can flow in and out of the low impedance inverting input. An internal amplifier senses the current flow and produces a voltage output proportional to the current. Current flowing out of the inverting input produces a positive output voltage. Current flowing into the inverting input produces a negative output voltage.
Noninverting input
+ Vin
Output Vo
Inverting input
Iin

Vo = Iin .Z(s)
Figure 3.7 Simple current feedback opamp model
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1111 2 + In Out 3 IINV 4 5 IINV 6 Rm Cc 7  In 8 9 1011 Figure 3.8 The small signal current feedback opamp 1 model 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 49111
3.3.1 AC performance The bandwidth relationship of a current feedback opamp can be explained by studying the amplifier in more detail. Figure 3.8 shows the smallsignal model. The input buffer has its output connected to a current mirror. When current flows from the buffer, out of the inverting input, an equal current flows out of the current mirror. A resistive load (Rm) across the current mirror converts the current flow into a proportional voltage. A small frequency compensating capacitor (Cc) is connected across Rm to ensure stability of the opamp. The voltage across Rm is output via a second buffer. The node equations for this model can now be worked out to find the frequency response. Since the input buffer forces the inverting input to have the same voltage as the noninverting input, V1 Vin. The voltage across Rm is V2 And I V1
R1
IRm 1 j CC R m
1 V – out R2 R2
1
And since Vout is a buffered version of V2, Vout V2. Now these can be combined to find Vout.
V R1 in
Vout
1 V – out Rm R R2 1 2 1 j CC Rm
If Rm >> R2, this can be simplified to: R2 Vout R1 Vin 1 j CC R2 1
The closedloop gain is 1 R2/R1, therefore: Vout AVCL Vin 1 j CC R2 When 1 2fCCR2, the closedloop gain falls by 3 dB, thus: f(–3dB)
1 2 CC R2
Thus the bandwidth is dependent upon R2 and the internal compensation capacitor. The bandwidth is not dependent upon R1 and is therefore not dependent upon the closedloop gain. If we consider the gain in terms of the complex impedance Z(s), we find:
VO R 1 2 VIN R1
1 1
1 LG
In this case loop gain (LG) is given by LG
Z(s) R2
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But what about the circuit design assumptions that were made for ideal opamps, in Chapter 1? Figure 3.9 shows a simple current feedback opamp model using the complex transimpedance Z(s), within a noninverting amplifier circuit. INPUT
+ In
OUT
IINV
OUTPUT
Z(s)
IINV –In R2 R1
If Z(s) >> R2, Vo/Vin ~ 1 + R2/R1
Figure 3.9 Noninverting amplifier with ideal current feedback opamp First consider what happens when the input voltage Vin is raised above 0 V. The input buffer responds to the increasing input voltage by raising the voltage at the inverting input. A current then flows out the inverting input. The current flow is sensed by the transimpedance stage and the output voltage rises. The output voltage ceases to rise when a balance is reached; this is when the current fed back through R2 is equal to the current flowing through R1. Feedback current thus replaces the current from the inverting input. In steady state conditions, the current from the input buffer can be very small; this is dependent upon the gain of the transimpedance stage. If the transimpedance stage has high gain (high Z(s)), the current from the inverting input can be assumed close to zero. The voltage gain of the input buffer is close to unity, which means that the differential voltage between inverting and noninverting inputs can be assumed to be close to zero. Thus the ideal model can be used to determine gain; in this case AVCL 1 R2/R1. In practice, the input buffer’s nonideal output resistance (Ro) will be typically about 20 to 40 , as shown in Figure 3.10. This additional resistance will modify the response, because the two input voltages will not be exactly equal while an error current flows. Some small voltage will be dropped across Ro. The additional resistance in the feedback path means that the loop gain will actually depend somewhat on the closedloop gain of the circuit. At low gains, R2 dominates, but at higher gains, the internal resistance has a greater effect and this reduces the loop gain, thus reducing the closedloop bandwidth. The transfer function of a nonideal, noninverting current feedback amplifier is given by:
R VO 1 2 VIN R1
1 1
1 LG
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INPUT
+ In
Z(s)
Ro –In
OUTPUT
OUT
IINV
IINV R2
R1
Ro reduces loop gain, hence overall gain
Figure 3.10 Noninverting amplifier with nonideal current feedback opamp Loop gain (LG) is modified by the introduction of Ro, and becomes: LG
Z(s)
R2 Ro 1
R2 R1
Ro 1 The gain error due to Ro is
R2 R1
Z(s)
Highfrequency circuits Current feedback opamps can be used in most applications where voltage feedback opamps are used. They have the advantage of having very high slew rates at low supply currents. Slew rates of 1000 V/s or more are common. The availability of high slew rates means that current feedback opamps are often found in video amplifier and cable driver circuits. The low impedance inverting input of a current feedback opamp allows fast transient currents to flow into the amplifier as needed. The internal current mirrors convey this input current to the compensation node, allowing fast charging and discharging. The actual slew rate will be limited by saturation of the current mirrors, typically at 15 mA. The overall slew rate is also limited by the slew rate limit of the input and output buffers. Using current feedback opamps in Sallen and Key low pass filters enables much higher frequencies to be used, compared to voltage feedback designs. However, the group delay of the opamp becomes significant if the 3 dB bandwidth of the opamp is less than ten times that of the filter. Sallen and Key filters usually use opamps as unity gain buffers. These have a direct connection between output and the inverting input. Current feedback opamps cannot be connected in this way because the inverting input of the opamp is actually the output of a buffer. Large amounts of current would flow between the two outputs if they were connected together.
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Instead a resistor can be connected between them, to limit the current flow. Alternatively, the opamp can be given some gain using feedback and shunt resistors. Note that the filter circuit component values are dependent upon the amplifier gain. Filter topologies that use reactive feedback, such as multiple feedback types, are not suitable for current feedback opamps. Sallen and Key filters are feasible because the opamp is used as a fixed gain block. In general, it is not desirable to add capacitance across the feedback resistor of a current feedback opamp circuit. Stability Current feedback opamps are like voltage feedback opamps, because they both suffer greater phase shifts at higher frequencies. Instability can be produced with phase shifts approaching 180°. Because the optimum value of R2 will vary with closedloop gain, opamp manufacturers usually supply a Bode plot and tables that give the bandwidth and phase margin for various gains. High values of closedloop bandwidth can be obtained at the expense of a lower phase margin, which results in peaking in the frequency domain, and overshoot and ringing in the time domain. With a voltage feedback opamp, shunt capacitance at the inverting input (CIN) generates an excessive phase shift that can lead to instability. The same effect occurs with a current feedback opamp, but the problem may be less pronounced. This is because the phase shift occurs at higher frequencies due to the inherently low impedance of the inverting input. Consider an amplifier circuit that employs a wideband voltage feedback opamp with R1 680 , R2 680 , and CIN 10 pF. The phase shift reaches 90° (and is thus unstable) at 1/[2CIN(R1//R2)], which is roughly 47 MHz. Let us now replace the voltage feedback opamp with a current feedback device having an inverting input resistance (Ro) of 40 . The frequency where 90° phase shift occurs is now given by 1/[2CIN(R1//R2//Ro)], this is about 445 MHz. If the unitygain bandwidth of both amplifiers is 500 MHz, the voltage feedback opamp will require a feedback capacitor for compensation. Although this will reduce the effect of CIN, it will also reduce the amplifier’s bandwidth. Using the current feedback device will give reduced phase shift, because the break point is about a decade higher in frequency. This means that the amplifier’s bandwidth will be greater because a compensating capacitor will not usually be required, unless to flatten the passband or to give optimum pulse response. 3.3.2 DC performance The DC gain accuracy of an amplifier using a current feedback opamp can be calculated from its transfer function.
R2 The gain error due to Ro is Ro 1 R 1 Z(s)
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Using a typical transimpedance of 1 M, a feedback resistor of 1 k, and an inverting input resistance of 40 , the gain error at unity gain is 0.004 per cent (basically Ro/Z(s)). At higher gains, gain accuracy degrades significantly. Current feedback amplifiers are rarely used for high gains, particularly when gain accuracy is required. For many applications, settling times are more important than gain accuracy. Although current feedback amplifiers have very fast rise times, many data sheets will only show settling times to 0.1 per cent. This is because of thermal settling tails, which are a major contributor to lack of settling precision. Thermal tails are caused by temperature differences between input stage transistors. Power dissipation of each transistor occurs in a very small area, which is too small to achieve thermal coupling between devices. Thermal errors are significant in noninverting circuits because these have a common mode input voltage and are thus more sensitive to differences in performance. Errors can be reduced by using the opamp in the inverting configuration, because the common mode input voltage is eliminated. Thermal tails do not occur instantaneously; the thermal coefficient of the transistors (which is process dependent) will determine the time it takes for the temperature change to occur and alter parameters – and then recover. Amplifiers do not usually exhibit significant thermal tails for input frequencies above a few kHz, because the input signal is changing too fast. Step waveforms, such as those found in imaging applications, can be adversely affected by thermal tails when DC levels change. For these applications, current feedback amplifiers may not offer adequate settling accuracy. One application that is difficult for current feedback opamps is an integrator circuit. The problem is that direct capacitive connection between the output and the inverting input can cause instability. Instability is a result of phase shifts in the feedback path. The frequency compensating capacitor produces up to 90° of phase shift. The gain and phase shift in the feedback circuit are frequency dependent due to the feedback capacitor. The circuit oscillates if the signal fed back to the inverting input approaches 180° at a frequency where the gain is greater than unity. The integrator circuit has to be modified to prevent instability when using current feedback opamps. A resistor (Rf) has to be inserted between the feedback capacitor (C1) and the inverting input. This resistor ensures that a minimum value of resistance is always in the feedback path, which limits the gain. A resistor (R2) in parallel with capacitor C1 determines the minimum frequency (Fc) at which the integrator is effective. Fc
1 2 R2C1
3.3.3 Current feedback noise considerations When amplifying low level currents, higher feedback resistance means higher signaltonoise ratio. This is because signal gain increases in proportion to R, whilst resistor noise increases in proportion to √R. Doubling the
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feedback resistor value doubles the signal gain and increases resistor noise by a only factor of 1.4. However, doubling the feedback resistor value causes the contribution from current noise to be doubled and the signal bandwidth to be halved. Therefore, the higher current noise of current feedback opamps may rule out their use in photodiode amplifier circuits. In circuits where noise is less critical, select the feedback resistor based on bandwidth requirements. If more gain is required, use a second stage. The number of applications for current feedback amplifiers will be limited because of current noise. The inverting input current noise can be about 30 pA/√Hz. However, the input voltage is somewhat lower than in voltage feedback opamps, 2 nV/√Hz or less. The feedback resistor will usually be under 1 k and, in a unitygain circuit, the dominant noise source will be the inverting input noise current flowing through the feedback resistor. Let the input noise current be 25 pA/√Hz in a unity gain circuit with a feedback resistor value of 680 , this gives 17 nV/√Hz noise at the output. If the input noise voltage is 2 nV/√Hz, the noise current is the dominant noise source. Let the gain of the circuit now be increased, by reducing the input resistor value. The output noise due to input current noise will not increase, because it is determined by the feedback resistor value. Now the amplifier’s input voltage noise will dominate. When the closedloop gain reaches 10, the contribution from the input noise current is only 1.7 nV/√Hz when referred to the input. The two noise sources are combined using the equation √(In2 Vn2) to give an inputreferred noise voltage of only 2.6 nV/√Hz (neglecting the resistor’s thermal noise). The current feedback opamp is thus useful in low noise amplifiers having a moderate gain.
3.3.4 Using current feedback opamps The inverting amplifier circuit works because of the low impedance node created at the inverting input. The summing junction of a voltage feedback amplifier (inverting input of the opamp) has low impedance. A current feedback opamp will operate very well in the inverting circuit because it has inherently low invertinginput impedance. The internal buffer holds the summing node at the same potential as the noninverting input. In the inverting circuit, voltage feedback amplifiers suffer from voltage spikes at the summing node in high speed applications. This is because the feedback loop takes time to settle and, until the loop has settled, the summing node impedance is not low. Current feedback opamps do not produce these voltage spikes because the summing node is low impedance irrespective of the feedback loop. Other advantages of the inverting circuit include maximizing the input slew rate and reducing thermal settling errors. Current feedback opamps can be used in currenttovoltage converters, by applying the input current into the opamp’s inverting input. There are limitations introduced by this arrangement: the amplifier’s bandwidth varies directly with the value of feedback resistance; and the inverting input current noise tends to be high.
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Although the inputs of a current feedback opamp are not matched, the transfer function for the ideal difference amplifier is still valid. At low frequencies, the differential amplifier’s CMRR is limited by the matching of the external resistor ratios, with 0.1 per cent matching yielding about 66 dB. At high frequencies, what matters is the matching of time constants formed by the input impedances. High speed voltage feedback opamps usually have wellmatched input capacitance, achieving a CMRR of about 60 dB at 1 MHz. Because the current feedback opamp’s input stage is unbalanced, the input capacitance will not be matched. Low value external resistors (100 to 200 ) must be used on the noninverting input of some amplifiers to minimize the mismatch in time constants. With careful attention given to resistor selection, an amplifier using a current feedback opamp can yield a high frequency CMRR equal to that obtained using a voltage feedback opamp. Both voltage feedback and current feedback amplifiers can further benefit from additional trimmer capacitors, but this reduces the signal bandwidth. If higher performance is needed, the best choice would be a monolithic high speed difference amplifier, such as the AD830. It requires no resistor matching and has a CMRR > 75 dB at 1 MHz, which reduces to about 53 dB at 10 MHz. Load capacitance presents the same problem with a current feedback amplifier as it does with a voltage feedback amplifier. It causes increased phase shift of the error signal, which results in reduction of phase margin and possible instability. The most popular method of dealing with capacitive loads is a resistor in series with the output of the opamp. The resistor should be outside the feedback loop, but in series with the load capacitance. A current feedback opamp also gives the option of increasing R2 to reduce the loop gain. All methods produce a reduction in bandwidth, slew rate and settling time. Care has to be taken with all circuit layouts to prevent instability. Stray and parasitic capacitance can reduce the phase margin and lead to oscillation. It is not a good idea to use sockets for the opamp; these increase the capacitance between device pins. Capacitance can be reduced by removing the printed circuit ground plane from the area around the input pins. Low value feedback resistors are advisable to reduce capacitive effects. Many current feedback opamps have recommended feedback resistor values quoted on their data sheets. Often graphs of frequency response versus feedback resistor values are given to show how the flatness of the response varies with resistance. As we know, the feedback resistor determines the bandwidth of the amplifier circuit.
3.3.5 Power supplies for current feedback amplifiers Current feedback opamps cannot be used for single supply operation. Opamps that are designed to deliver good current drive and have a voltage swing that approaches the supply rails usually use common emitter output stages, rather than the usual emitter followers. Common emitter circuits allow the output voltage to swing almost to the supply rail (less the output transistor’s collector–emitter saturation voltage). This type of output stage is slower than emitter followers, due to the increased circuit complexity and
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higher output impedance. Because current feedback opamps are specifically developed for the highest speed and output current, they feature emitter follower output stages. Higher speed processes have produced a common emitter output stage with 160 MHz bandwidth and 160 V/s slew rate. An example of a device using this technology is the ‘Analog Devices’ AD8041. This voltage feedback opamp is powered from a single 5volt supply. Single supply input stages use pnp differential pairs. This arrangement allows the common mode input range to extend down to the lower supply rail (usually ground). Such an input stage is impossible with current feedback opamps. Note that even in circuits using ‘railtorail’ voltage feedback devices, the output voltage will not be near the supply rails if driving a low impedance load; this is due to the voltage drop across the output stage’s internal resistance. Current feedback opamps can be used in single supply circuits provided that the input and output voltages are not allowed to approach the supply rails. This may require level shifting or AC coupling. The noninverting input must be biased to the middle of its working range, but this is already a requirement in most single supply systems. Decoupling capacitors across the power supplies are very important. As with all high frequency circuit design, capacitors suitable for all encountered frequencies are needed. As a rule of thumb, a 10 F tantalum capacitor in parallel with a 10 nF or 100 nF ceramic capacitor should be used. The capacitors should be connected close to the opamp’s power supply pins.
Exercises
3.1 In an inverting amplifier circuit, using a current feedback opamp, the transimpedance is 1 M and the feedback resistor R2 is 750 . Find the loop gain (LG). Resistor R1, connecting the inverting input to ground has a value 100 . What is the closedloop gain VO/VIN at low frequencies? (Assume an ideal amplifier.) 3.2 The circuit in Exercise 3.1 is now used with a nonideal amplifier, having a noninverting input resistance of Ro 30 . What is the closedloop gain VO/VIN in this case? What is the gain error due to the introduction of Ro? 3.3 A current feedback amplifier has a voltage noise of 2 nV/√Hz and inverting input current noise of 25 pA/√Hz. With a feedback resistor of 750 and a gain of 20, what is the input referred noise?
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4 Applications: linear circuits 4.1 Introduction
This chapter concentrates on linear circuit applications, including inverting and noninverting amplifiers, differential amplifiers, buffers, currenttovoltage converters and voltagetocurrent converters. Modifications to these basic circuits can be found in later chapters. A further collection of opamp circuits will be found in Appendix A1. The usefulness of the opamp approach is the many variations of a basic circuit that are possible. Opamps are used extensively in analogue circuit design. The approach involves breaking down the circuit, or system function, into a series of specific operations. A separate opamp circuit can then perform each operation. The requirements of each circuit may vary considerably, but the specific operations required in the different systems are common to many systems. The designer should be able to pick out, from the many circuits given, those appropriate to their own particular system. The circuits presented in this chapter do not generally refer to particular opamp devices. Most applications will function with any opamp type. The particular opamp used in a circuit determines the errors and performance limits of the application. In order to make a working circuit from those given in the text, all that is normally required is to add power supply connections to the opamp. Only those applications requiring very low noise, or wide bandwidth, or very fast slew rate, will normally require the use of more specialized (and more expensive) opamps. Passive external components are connected to the opamp in order to define a precise circuit operation. The circuit designs given do not generally give component values, and the designer must choose these for himself. As a general guideline to resistor value selection, choose the lowest value that does not significantly load the opamp’s output. Most opamps are designed to supply a load at their output terminal that should be no less than 1 k. Large input resistor values increase the offset errors due to bias current (see Chapter 2); and they are shunted by stray capacitance, which limits the operating bandwidth. It should be remembered that the feedback resistor also contributes to the opamp’s load. The effective load is the parallel combination of an external load and feedback resistor. In inverting amplifier circuits, the inverting input of the opamp is effectively at earth potential. The input resistors provide a load to the signal source, and their value must be chosen with care. In some instances, impedance matching may be required and the input resistor should have a value equal to the characteristic impedance (often equal to the source impedance). Most often, input resistors are chosen to have a higher value than the input signal source, so that they do not significantly load it.
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Ideal forms of the basic voltage scaling and buffer circuits have already been dealt with in Chapter 1. The circuits are for convenience shown again in Figure 4.1. (a)
(b) (c)
eo = 1+
R2 R1
ei
Figure 4.1 Basic voltage scaling applications (a) Inverting amplifier. (b) Noninverting amplifier. (c) Unitygain follower (buffer) The great attraction of all opamp circuits lies in the ability to set a precise operation with a minimum number of precise components. In Figures 4.1(a) and (b), closedloop gain is determined by simply selecting two resistor values. The accuracy of this gain depends almost entirely upon the resistor value tolerance. The inverting circuit in Figure 4.1(a) can be given any gain from zero upwards. The lower limit of the gain for the noninverting circuit Figure 4.1(b) is unity. In both configurations, the practical upper limit to the gain depends on the requirement for maintaining an adequate loop gain, so as to minimize gain error (see Section 2.3.1). Also, closedloop bandwidth decreases with increase in closedloop gain. If high closedloop gains are required, it is often better to connect two opamp circuits in cascade rather than to use a single opamp circuit. Both inverting and noninverting amplifier circuits feature low output impedance. This is a characteristic of negative voltage feedback (see Chapter 2).
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The main performance difference between them, apart from signal inversion, lies in their input impedance. In the case of the inverter, resistor R1 loads the signal source driving the circuit. The noninverting amplifier presents very high input impedance, which ensures negligible loading in most applications. The main limitation of the inverting circuit is that its input impedance is effectively equal to the value of the input resistor R1. The application may require high input impedance, to minimize signal source loading. This demands a large value for the resistor R1 and an even larger value for R2, dependent upon the gain required. Large resistor values inevitably give increased offset errors due to opamp bias current. Also, stray capacitance in parallel with a large feedback resistor limits bandwidth. For example, assume that it is required to use the inverting circuit with closed loop gain 100 and input resistance 1 M. In Figure 4.1(a) R1 1 M and R2 100 M is required. Stray capacitance Cs in parallel with R2 would limit the closedloop bandwidth to a frequency f 1/(2CsR2). With Cs say 2 pF, the closedloop bandwidth would be limited to 800 Hz – a severe restriction! Stable very high value resistors are not freely available. If the inverting configuration must be used, the need for a very high value feedback resistor can be overcome by the use of a T resistance network as shown in Figure 4.2. This is at the expense of a reduction in loop gain and an increase in noise gain (1/).
Figure 4.2 Inverter circuit using resistive T feedback network The noninverting circuit achieves high input impedance without the use of large value resistors. This is an advantage in applications requiring wide bandwidth, since large value resistors and stray circuit capacitance interact to cause bandwidth limitations. The effective input impedance of the noninverting configuration was described in Section 2.3.3. This was shown to be equal to the differential input impedance of the opamp, multiplied by the loop gain in the circuit (ZinAOL). Practical opamps have their common mode input impedance Zcm between their noninverting input terminal and
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earth. This shunts ZinAOL and so reduces its value. The effective input impedance of the follower configuration is thus Zcm. The high input impedance of the noninverting circuit makes it a better choice than the inverting circuit for use in many applications. However, the noninverting circuit is subject to common mode errors (see Section 2.11). Also, the voltage applied to the noninverting input must not be allowed to exceed the maximum common mode voltage for the opamp (since feedback will force both inputs to have the same potential). These points do not usually impose too serious a restriction. The buffer circuit in Figure 4.1(c) has high input impedance and low output impedance. It is often used to prevent interaction between a signal source and load, e.g. for unloading potentiometers, or buffering voltage references. Buffers are used in Sallen and Key filter circuits (see Chapter 9) to prevent interaction between filter stages and to allow simple design rules.
4.2.1 Variable gain control Instead of using fixed value resistors to set the gain, potentiometers may be used to give variable gain control. The arrangement shown in Figure 4.3(a) allows a variation of gain from zero to a very high value. However, the scaling factor does not vary linearly with respect to potentiometer rotation. A second disadvantage is that the input impedance falls as the gain is increased. The circuit of Figure 4.3(b) gives a narrower range of scale factor variation from zero to R2/R1, but the gain variation is linear with respect to potentiometer setting and the input impedance remains constant (equal to R1). (a)
(b)
Figure 4.3 Variable scale factor. (a) Nonlinear gain control. (b) Linear gain control
Changing the closedloop gain inevitably changes the closedloop bandwidth. Also, changes in the values of gain setting resistors produce a change in the offset error due to opamp bias current. Offset errors due to bias current can be minimized by using a low bias current FET input opamp.
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4.2.2 Switched scaling factor Gain setting resistors can be switched into circuit. Different values of scale setting resistors are switched into the signal path, thus allowing switching of the gain between preset values. Switching can be performed by a manual control of a mechanical switch, by an electromechanical switch or by means of some form of solid state switch. The circuit given in Figure 4.4 illustrates the use of an analogue switch in a programmable gain circuit.
Figure 4.4 Programmable gain operational amplifier 4.2.3 Voltage controlled gain Voltage control of an opamp’s gain requires a voltage controlled resistive element. Junction gate FETs when operated below pinchoff behave as linear resistors with channel resistance (rds) determined by the value of the gate source voltage. For small values of drain source voltage they exhibit a bilateral characteristic. Linear voltage control of gain can be obtained by using a feedback arrangement between the drain and gate of the FET. The voltage swing across the FET can be kept small by including it in a Tnetwork as shown in the circuit of Figure 4.5. The effective resistance of the resistive T when connected to the opamp summing point is Re R2 R3
R2R3 rds
Where rds is the drain source resistance of the FET, which is determined by the relationship
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Figure 4.5 Voltage controlled scaling factor rds
ro V 1– c 2Vp
where: ro is the drain source resistance for Vds 0; Ids 0, Vp is the pinchoff voltage and Vc is the control voltage applied to the gate of the FET via a series resistor. Substitution gives
R2R3 1 – Re R2 R3
Vc 2Vp
ro
Which is a linear function of Vc. The closedloop signal gain of the circuit, Re/R1, also varies linearly with the value of Vc. The range of gain variation obtainable depends upon the r0 of the FET used in the circuit. A practical circuit with the component values shown in Figure 4.5 gives the gain control shown by the graph.
4.3 Voltage summation
The voltage summing property of an ideal opamp has been treated in Chapter 1. The behaviour of a practical summing circuit is now discussed.
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Figure 4.6 Voltage summation A summing configuration is shown in Figure 4.6. In this circuit the input signals are effectively isolated from one another by the ‘virtual earth’ at the inverting input terminal of the opamp. Some consideration has to be given about the resistor values used in this circuit. The resistors should have a high enough value to prevent signal source loading, but low enough to prevent input bias current from causing offset errors. If large values of input resistor are necessary, use a low bias current FET input opamp in order to minimize the offset error. In the ideal circuit there is no limit to the number of input voltages that can be summed, but in the practical circuit the number of inputs is limited by the need to maintain an adequate loop gain. All paths to the inverting input terminal of the opamp should be taken into account when assessing loop gain, closedloop signal bandwidth and drift error. Note that the closedloop gain 1/ for the circuit is Rf 1 1 R1 // R2 // R3
(4.1)
A differential amplifier circuit is commonly used to amplify or buffer differential signals whilst rejecting common mode signals. A differential signal is presented across two terminals; the voltage on one terminal rises as the voltage on the other terminal falls (relative to earth). A common mode signal is one where the voltages on both terminals rise and fall together. An example use of a differential amplifier is terminating transmission lines where signals common to both wires are due to induction from external sources, such as mains power supplies. In many cases, the wanted differential signal is smaller in amplitude than the common mode signal, but the differential amplifier is able to extract the wanted signal because of the common mode rejection by the amplifier. Differential amplifiers also allow one signal to be subtracted from another. Figure 4.7 shows the type of circuit configuration that is employed. An ideal
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Figure 4.7 Single opamp differential amplifier analysis of this circuit was given in Chapter 1; some of its practical limitations are now discussed. A prime requirement of a differential input amplifier circuit is that it should have a high common mode rejection ratio (CMRR). According to the ideal performance equation of the circuit in Figure 4.7, the output is zero if the two input signals e1 and e2 are equal. The ideal circuit has an infinite CMRR – not the case with practical circuits. In a practical circuit any mismatch in the resistor ratio values connected to the opamp input terminals causes a common mode signal (e1 e2 ecm) to inject a differential signal to the amplifier. This differential signal is amplified to produce a nonzero output signal. CMRR is thus degraded unless the resistor values are exactly matched. In assessing the common mode characteristics of differential amplifiers, care must be taken in distinguishing between the characteristics of the circuit and those of the opamp used in it. The CMRR of the circuit is defined as: CMRR
Differential gain of circuit Common mode gain of circuit
(4.2)
In the circuit of Figure 4.7, CMRR depends both upon resistor matching and upon the CMRR of the opamp. The CMRR of the circuit due to resistor mismatch using resistor values with tolerance x is in the worst case: R2 R1 4x
1 CMRR (due to resistor tolerance)
(4.3)
(see Appendix A3) For example, a single opamp differential input circuit (such as Figure 4.7) with differential gain 10 (R2/R1 10), using resistors of 1 per cent tolerance (x 0.01) in the worst case has: CMRR (due to resistor tolerance) 11/0.04 2.75, or 49 dB The overall CMRR of the circuit due to both resistor mismatch and the finite CMRR of the opamp is:
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Total CMRR
CMRR(R) CMRR(A) CMRR(R) ± CMRR(A)
(see Appendix A3)
The common mode errors due to the two effects may be of the same or opposite sign, so that the total CMRR may be greater than or less than the CMRR of the opamp used in the circuit. It is of course possible to trim one of the external resistors in Figure 4.7. This enables the common mode gain, due to resistor tolerance, to be equal in magnitude but opposite in sign to the common mode gain of the circuit (due to the noninfinite CMRR of the opamp alone). In theory, an infinite CMRR can be attained in this way. In practice, resistor trimming can give a 10 to 100 times increase in CMRR for the circuit over the CMRR of the opamp used in it. A high CMRR achieved in this way is unfortunately not maintained: resistor values change with temperature, and also the CMRR of an opamp does not remain stable. In many applications a requirement of differential input amplifiers is that they have high differential and common mode input impedance. The input impedance of the circuit in Figure 4.7 is determined by the resistor values. Its differential input resistance is 2*R1 and it has an effective common mode input resistance at each input point of R1 R2. If large resistor values are used in the circuit, to give a high input resistance, this can have side effects. One effect is stray capacitance that causes degradation in CMRR at the higher frequencies. Another effect is to give an increased offset error because of opamp bias current. The single opamp differential amplifier has limitations in its performance. Despite this, it is often used (because of its simplicity) in noncritical differential applications. Improved performance can be obtained with circuit configurations using two or more opamps; or by using application specific integrated circuits which have the functionality of differential amplifiers. The circuit shown in Figure 4.8 is a differential input amplifier. It uses two coupled followers to attain high input impedance without the use of high value resistors. It also provides the possibility of gain setting with a single resistor. Treating each opamp and its associated input and feedback resistors separately, we can derive the ideal performance equation for the circuit in Figure 4.8. Analysing the circuit we can see that opamp A2 has two input signals applied to it. These are signal e2 and the output from A1, which is signal e1 multiplied by [1 R1/R2]. The output of A2, due to input e1 alone, is the signal from A1 multiplied by R2/R1 (see Chapter 2). Thus the output from A2, in terms of input e1, is:
eo′ e1 1
R1 R2
–RR 2
1
Now considering the output from A2, due to input e2 alone, we have:
eo′′ e2 1
R2 R1
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Figure 4.8 High input impedance differential amplifier The total output from A2 (eo), in terms of inputs e1 and e2 applied together, is found by adding the two expressions: eo eo″ eo′
eo e2 1
R2 R – e1 1 1 R1 R2
RR 2 1
This becomes:
eo (e2 – e1) 1
R2 R1
(4.4)
A practical circuit based upon Figure 4.8 has a CMRR that depends upon both resistor tolerances and upon the CMRR of the opamps used in it. The input common mode range for the circuit is equal to that of the opamps. With the gain setting resistor R3 in circuit the output voltage in the ideal case is determined by the equation:
eo (e2 – e1) 1
R2 R 2 2 R1 R3
(4.5)
In deriving this equation it should be remembered that, with R3 in circuit, R2 and the parallel combination of R1 and R3 now determine the value of 1/ for opamp A2. Another differential amplifier configuration that is often used is shown in Figure 4.9. This circuit has two stages: a differential input stage and a subtractor stage. The differential input stage presents high impedance to both inputs.
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eo1
eo = 1 + 2
R2
R4
R1
R3
[e2 – e1]
eo2
Figure 4.9 High input impedance differential amplifier configuration Two coupled noninverting amplifiers form the differential input stage. This stage produces a differential output voltage in response to a differential input signal. Assuming that the opamps in the input stage take no current at their input terminals, the same current must flow through the three resistors (labelled R1 and R2). If we make the further usual assumption of negligible voltage between opamp input terminals then this current I
eo1 – e1 e1 – e2 e2 – eo2 R2 R1 R2
R2 R e1 – 2 e2 R1 R1
R2 R e – 2e R1 2 R1 1
Thus eo1 1 And eo2 1
The input stage has a differential output, given by:
(eo1 – eo2 ) (e1 – e2 ) 1 2
R2 R1
(4.6)
Note that if e1 e2 ecm then eo1 eo2 ecm. The input stage passes common mode input signals at unity gain. If the input stage used separately connected follower circuits, these would pass both common mode and differential signals at the same gain. The advantage of a crossconnected differential input stage, which is configured to provide some voltage gain, is that it amplifies differential input signals but not common mode signals. An isolated load, such as a meter, can be driven directly by the differential output from the input stage. This has a theoretically infinite CMRR unaffected by resistor tolerance and the possibility of gain setting by means of a single resistor value (R1). In practice CMRR is not infinite, because of differences in the internal common mode errors of the two opamps. Dual opamps can be used in this type of circuit, with the possibility of drift error
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cancellation (if the temperature drift coefficient on the two opamps matches and tracks). Monolithic dual opamps have the advantage of maintaining both opamps at the same temperature. However, despite the monolithic construction, the opamp parameters are not matched. Improved performance can be obtained by using dual opamp devices in which two separately matched opamp chips are assembled into a single dualinline package. To drive an earthreferred load, a single ended output is required. The differential output produced by the crosscoupled followers can be converted into a single ended output by using the differential amplifier circuit of Figure 4.7, which uses a single opamp. The overall CMRR obtained with a circuit that uses three opamps is greater than that of the single opamp circuit, by a factor equal to the differential gain of the input stage. The resistor values in the single opamp circuit should be well matched, to give good common mode rejection. The input common mode range of the circuits of Figures 4.8 and 4.9 is limited to that of the opamps used in the circuits. A differential input circuit configuration using two inverting amplifiers (see Appendix A1, Figure A1.2) can be given a larger input common mode range but with the disadvantage of lower input resistance in the inverter configuration. In the presence of large or potentially dangerous common mode signals, consideration should be given to the use of an isolation amplifier.
4.5 Current scaling
The opamp circuits considered up to now are suitable for scaling input signal voltages. In many systems there is a need to scale the output from current sources, such as lightsensitive diodes. Lightsensitive diodes provide a reverse leakage current proportional to the light intensity at their pn junction. The circuits considered in this section are designed to process an input current, rather than an input voltage.
4.5.1 Currenttovoltage conversion In Chapter 1, it was shown that an ideal opamp could provide an ideal, zero voltage drop, currenttovoltage conversion. There are two things that must be considered: (1) the possibility of closedloop instability and (2) the reduction of drift errors that determine conversion accuracy. (1)
Closedloop stability
In practice, the stability problem does not usually present too serious a difficulty. An externally connected capacitor Cf (see Chapter 2) connected in parallel with the scaling resistor Rf normally assures closedloop stability. The importance of offset is dependent upon the size of the current to be measured and the processing accuracy required. In Figure 4.10, an opamp currenttovoltage converter is supplied with signals by a current source. Stability is determined by the source capacitance. Source capacitance causes a phase lag in the feedback signal at the higher
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without Cf
with Cf
Figure 4.10 Currenttovoltage converter–stability analysis frequencies, which can lead to insufficient phase margin. Closedloop stability is most conveniently examined in terms of the appropriate Bode plots. The Bode plot for 1/ is superimposed upon the openloop Bode plot in order to examine the frequency dependence of the magnitude and phase of the loop gain (see Chapter 2). The value of 1/ for the circuit of Figure 4.10 without the capacitor Cf in the circuit is
1 R 1 f [1 j Cs (Rs // Rf )] Rs
(4.7)
This breaks up at the angular frequency c Cs(Rs//Rf). If this frequency occurs before the frequency at which 1/ and AOL intersect, the two plots
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will have a rate of closure of 40 dB/decade. This means that there may be insufficient phase margin. Note that at frequency 1 the phase shift in is tan1(1/c) and the phase margin in the circuit is 90° (see Chapter 2). If Cf is connected in circuit it introduces a phase lead into the feedback loop which offsets the lag due to Cs . With Cf in circuit, the value of 1/ becomes
1 R 1 f Rs
1 j (Cs Cf) (Rs //Rf) 1 j Cf Rf
(4.8)
The (1/) log(f ) plot breaks back at the angular frequency 1/(Cf Rf) and if this frequency is suitably chosen the 1/ and AOL plots close at 20 dB/decade thus ensuring an adequate phase margin. The closedloop signal bandwidth is fixed by the value used for Cf at the frequency f 1/(2Cf Rf). (2)
Conversion accuracy
In many practical applications of the currenttovoltage converter, Rs will be greater than the value of the scale setting resistor Rf, making the value of 1/ approximately unity at low frequencies. If the impedance of the source current is lower than Rf, the noise gain 1/ will be greater and the loop gain smaller. Consequently, there will be a decrease in accuracy, and an increase in drift error due to opamp input offset voltage temperature dependence. Offset and drift error may be estimated by applying the general method outlined in Section 2.10.4. An expression for the total equivalent input offset voltage is: Eos Vio (Rf // Rs)Ib This appears at the output multiplied by 1/. Output offset voltage Eos(1 Rf /Rs) In order to assess accuracy this may be referred to the input (by dividing by Rf) as an equivalent input error current.
Ios 1
Rf Eos Vio ± Ib– Rs Rf Rs //Rf
Opamp bias current is normally the main error component. The large resistor values commonly used in currenttovoltage converters make the error due to opamp input offset voltage negligible. Initial offset can be zeroed using a high value resistor, to feed a small adjustable current to the inverting input terminal of the opamp. The temperature drift of the opamp bias current is then the limiting factor in determining accuracy. A low bias current opamp should be chosen for accurate measurements of small currents, e.g. a FET input type. Measurement of currents in the picoamp range requires particular attention to the avoidance of stray leakage currents otherwise the performance capabilities of low bias current opamps cannot be realized (see Section 9.4).
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High value resistors are necessary to set the scaling factor in small current measurements. Unfortunately, high value resistors tend to be less stable than commonly available devices. Sensitivity of the circuit can be increased without using very high value resistors by using a resistive T network as shown in Figure 4.11, but note that this is at the expense of a decrease in loop gain and an increase in offset and noise gain.
Figure 4.11 Resistive T network gives increased sensitivity without high value feedback resistor The transfer function for this circuit can be derived from consideration of currents in the feedback loop; see Figure 4.12. Negative feedback forces the opamp’s inputs to be at the same (earth) potential. A voltage at the output, eo, causes current Io to flow through R2 and the parallel combination of R1 and Rf. Thus:
eo Io R2
R1Rf R1 Rf
(4.9)
Current Io flows through the parallel combination of R1 and Rf. The share passing through Rf is equal to Iin, but with opposite polarity, since no current flows into the opamp’s inverting input. The current through Rf is given by: – Iin Io
R R R 1
1
f
Transposing this to find Iin in terms of Io, we get: Io Iin
R R R 1
f
(4.10)
1
Combining equations 4.9 and 4.10, we get: eo – Iin
R R R R RRRR 1
f
1 f
2
1
eo Iin
1
f
R R R [R R ] 1
f
2
f
1
eo Iin R2 Rf
R2Rf R1
(4.11)
+ _
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A currenttovoltage converter overcomes the problem of the finite resistance of movingcoil meters when used for current measurement. Possible circuit configurations are shown in Figure 4.13. Battery operation of the opamp allows nonearth referred measurements to be made as in Figure 4.13(c). Note that equation 4.10 is used, except that Rf is replaced by R2 and Io becomes Im. What was R2 in Figure 4.11 is now the meter resistance, which does not affect the transfer function. – Io Im Iin
R1 R2 R Iin 1 2 R1 R1
(a)
(b)
(c)
Figure 4.13 Current measurement circuits. (a) Simple measurement. (b) Current measurement with increased sensitivity. (c) Current measurement not referred to earth (battery supplies)
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4.5.2 Current summation The basic currenttovoltage converter circuit of Figure 4.11 can be used to sum currents to earth from separate signal sources. All that is required is to add the extra input paths to the inverting input terminal of the opamp. The circuit shown in Figure 4.14 illustrates the principle. In order to ensure adequate phase margin, the value required for the feedback capacity Cf is now governed by the total capacitance to ground at the inverting input terminal (Cs1 Cs2 etc.).
Figure 4.14 Current summing circuit
4.5.3 Current differencetovoltage conversion Opamps allow the measurement of current with no voltage drop in the measurement circuit. Current is supplied to the inverting input terminal of an opamp and its noninverting input terminal is earthed. The feedback resistor provides a path for the current whilst the inverting terminal is held at earth potential. A current difference measurement requires the use of two opamps in order to satisfy the zero voltage drop criterion. The circuit shown in Figure 4.15 combines the summing property of one opamp with a current inversion performed by a second opamp. Opamp A2, with equal value resistors (R1) connected between its output and its two input terminals, forces equal currents to flow towards its two input terminals in order to maintain them at the same potential. The inverted current I2 is supplied to the summing opamp A1 via a very high effective output impedance obtained as a result of the positive feedback applied to amplifier A2. In cases where a voltage intrusion into the measurement circuit is allowable, a single opamp can be used to perform a current difference conversion. The circuit shown in Figure 4.16 gives an output voltage that is proportional to the difference in the two input currents, I1 and I2. Note that, in this circuit, a voltage drop, V I2R, is introduced into the measurement path. This voltage drop represents a common mode input to the amplifier. Subtraction of equal input currents requires accurate matching of resistor values.
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Figure 4.15 Current differencetovoltage conversion
Figure 4.16 Single opamp for current differencetovoltage conversion
4.6 Voltagetocurrent conversion
Some loads require a current drive rather than a voltage drive. In such cases, an opamp circuit configuration is required that will give a linear voltagetocurrent conversion. Voltage controlled current sources are very useful in a variety of measurement applications, such as resistance measurement. They can also be used to drive inductive loads for the production of controlled magnetic fields. There are several ways in which an opamp may be used to produce a voltagetocurrent conversion. The circuit configuration adopted is determined by the operating requirements of the load. For example, is the load to be earthed or can it float, is a unidirectional or bidirectional current drive required?
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4.6.1 Voltagetocurrent converters – floating load The simplest currenttovoltage converter circuits are those for which the load is allowed to float. Basic inverting and noninverting voltagetocurrent converters are illustrated in Figure 4.17. In each case the ideal performance equation, I ein/R1, follows directly from the usual ideal opamp assumptions. In the inverting configuration the input signal source must supply a current equal to the load current. In the noninverting circuit, negligible current is drawn from the signal source but common mode limitations and errors must be considered.
Figure 4.17 Simple voltagetocurrent converter load floating In all voltagetocurrent conversions, the opamp used in the circuit must be capable of providing the desired maximum load current. Also, the output voltage that is required for maximum load current must not exceed the opamp’s rating. Remember that some form of booster circuit (see Chapter 9) can always increase opamp output limits. Inductive loads (coil driving) require particular attention, in terms of the opamp’s maximum output limits and in achieving closedloop stability. An inductive load introduces an extra phase lag in the feedback loop. This can lead to an inadequate phase margin, even when the opamp used in the circuit is frequency compensated for unitygain operation. Closedloop stability can often be achieved by connecting a resistor in series with the inductive load, and by adding a lead capacitor directly between opamp output and phase inverting input. Bandwidth is inevitably limited by these added components.
4.6.2 Voltagetocurrent converters – earthed load Simple circuits can be used for current drive of an earthed load provided that either the controlling input signal voltage or the power supplies to the opamp can be floated. The input signal must float in the circuit of Figure 4.18. Negative feedback forces the differential input terminals of the opamp to be at the same potential and in doing so produces a voltage across the resistor R that is equal to ein. The current through R, except for the small opamp bias current, passes through the load, and there is negligible loading
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Figure 4.18 Voltagetocurrent converter floating signal source of the input voltage signal. Note that the voltage that appears across the load represents a common mode input voltage to the amplifier and common mode limitations and errors must therefore be considered.
4.6.3 Voltagetocurrent converter – earthed load and power supplies The circuit shown in Figure 4.19 can be used to supply a bidirectional current to an earthed load.
Figure 4.19 Voltagetocurrent converter (earthed load and power supplies) In the circuit of Figure 4.19, the current is controlled directly by a single ended input voltage. Making use of the usual ideal opamp assumptions, we can derive the ideal performance equation for the circuit. Thus the signal at the inverting input terminal is: e– ein
R2 R1 eo R1 R2 R1 R2
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and the signal at the noninverting input is: e [eo – IoR5]
R4 R3 R4
It is assumed that [R3 R4] >> R5//RL. The opamp forces e e. Resistor values are chosen so that R2/R1 R3/R4. Making these substitutions the performance equation simplifies to: Io –
ein R2 R5 R1
The offset error for the circuit when referred to the signal input is:
Vin(offset) Eos 1
R1 R2
where Eos ±Vio IbRs IbRs (see Chapter 2). The load current is supplied by very high effective impedance. The value of this impedance depends upon accurate matching of resistor ratios in the circuit. Accurate matching of resistor ratios provides stability of load current against fluctuations in load impedance. Trimming the value of resistor R4 (by the use of a small potentiometer in series with it) allows the circuit to produce near constant output current with variations in load. A preferable alternative to a trimming potentiometer would be to use close tolerance ( e1; I2 k2(ei e2), for ei > e2; I3 k3(ei e3), for ei > e3; etc. In the circuit shown in Figure 5.3, the break points, e1, e2, e3, . . ., etc. are each set by a diode, a resistive divider, and a reference voltage supply. The input voltage is connected to these networks. The reference voltage polarity and the diode orientations shown are appropriate to a positive input signal.
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Figure 5.3 Synthesized nonlinear response Diode D1 becomes forward biased when the input voltage exceeds the first break point e1 Eref (Ra1/Rb1 ). Feedback from the amplifier output, through the resistor R, holds the inverting input terminal of the amplifier at earth potential. Neglecting the diode voltage drop, the current through diode D1 for values of the input voltage greater than the first break voltage e1 is thus I1
1 (e – e ) Ra1 i 1
Similar reasoning gives the values of the currents through D2, D3, . . ., Dn, as In
1 (e – e ) Ran i n
The values for the break voltages are given by en Eref
Ran Rbn
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The slopes of the straightline segments used to approximate the desired function are Sn R
R
1
a1
1 1 ... Ra2 Ran
Negative input signals may be handled by using additional input networks, with diode and reference voltage polarities reversed. Nonmonotonic functions can be generated by the use of an additional opamp to invert the polarity of the input signal. Input networks with appropriate diode and reference voltage polarities must follow the opamp. This simple treatment has neglected diode voltage drops. Practical diodes exhibit a nonzero forward voltage drop with the added complication of temperature dependence. By using additional opamps, diode effects can be reduced to negligible proportions and give break point voltages that change insignificantly with temperature. The circuit shown in Figure 5.4 illustrates a method of reducing diode effects. The opamp diode combinations used in the input network act essentially as precision rectifiers (see Chapter 8). Break point voltages are determined by Eref, resistors Rc and resistors Rb1, Rb2, . . ., Rbn, and en Eref
Rc Rbn
The slopes of the line segments are determined by resistors Re1, Re2, . . . , Ran, and Sn R
R1
a2
1 1 ... Ra2 Ran
The circuit shown in Figure 5.5 illustrates another method of producing temperature stable break points. The external transistors should all be of the same type and have a high current gain. In the circuit of Figure 5.5, the gain for small output signals is R2/R1. Transistors Tr2 and Tr3 are conducting, but feed back very little current to the amplifier summing point. When the output voltage rises to a certain level (set by R3, R4 and Vs), transistor Tr2 saturates and effectively connects R3 in parallel R2. This makes the gain of the circuit reduce to: Gain
R2 // R3 R1
When the output voltage rises further, to a level set by R5, R6 and Vs, saturation of transistor Tr3 occurs and connects R5 in parallel with R3 and R2. The gain is thus reduced further to: Gain
R2 // R3 // R5 R1
Temperature compensation is achieved in the circuit by the inclusion of transistors Tr1 and Tr4. Transistor Tr1 is used to temperature compensate the baseemitter voltages of Tr2 and Tr3. This arrangement keeps the voltage
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Figure 5.4 Nonlinear amplifier, break points stabilized across the feedback resistors R3 and R5 equal to the output voltage across the feedback resistor R2. Transistor Tr4 is used to provide temperature compensation for change in saturation voltage of the transistors Tr3 and Tr2.
5.3 Logarithmic conversion with an inherently logarithmic device
The nonlinear effects of diodes and transistors are often used to obtain logarithmic amplification. The logarithmic performance obtained using an opamp with nonlinear components is influenced by the characteristics of both the amplifier and the nonlinear component. Therefore, an understanding of accuracy limitations requires some knowledge of the nonlinear component.
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Figure 5.5 Nonlinear amplifier with temperature compensated break points Shockley’s first order theory for a single pn junction gives the relationship I Io (eqV/kT – 1)
(5.1)
where: I is the current through the junction (A), Io is the theoretical reverse saturation current (A), V is the voltage across the junction, q is the magnitude of the electronic charge (1.6 1019 C), k is Boltzmann’s constant (1.38 1023 J/K) and T is the temperature in Kelvin. Substituting values of constants gives kT/q ~ 26 mV at 27°C; thus for values of V greater than say 100 mV the exponential term in equation 5.1 predominates and we may write: I Io eqV/kT (V > 100 mV) Now, by taking natural logarithms: ln
II qV kT o
hence V
I kT ln q Io
To give this result in terms of logarithms to base 10, i.e. log(I/Io), we use the mathematical relationship log(x) ln(x)/ln(10), where log(x) is to the base 10.
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ln
Thus, log10
I I
II ln(10) and ln(10) log II lnII o
10
o
o
o
Note that ln(x) 2.3 log10(x), because ln(10) 2.3. In terms of diode junction voltage, we have: V 2.3
I kT log10 q I10
(5.2)
According to equation 5.2, a plot of log(I) against V gives a straight line of slope 2.3 kT/q volts per decade of current change. (Note the factor 2.3 kT/q ~ 60 mV at 27°C.) A diode, which is assumed to obey equation 5.2, is shown connected as the feedback element in the circuit illustrated in Figure 5.6.
Figure 5.6 Log amplifier with a diode as log element
Referring to the circuit in Figure 5.6, and assuming ideal opamp performance: V
–R1 eo kT I log10 2.3 R1 R2 q Io
or eo – 2.3
R R R
kT I log10 q Io
1
2
(5.3)
1
The input current in the circuit shown is I ei/R. In the derivation of equation 5.3 we neglect the loading effect of the current, I, on the resistive divider R1 and R2. This divider is used to set a convenient scaling factor. The 60 mV/decade current change is a somewhat inconvenient factor, and a 1 V/decade scaling factor is usually preferred. The circuit given in Figure 5.6 is attractively simple but is unfortunately rather limited in performance. Even assuming the availability of diodes that accurately obey equation 5.1, there remains the problem of temperature dependence. The scaling factor of 2.3kT/q is linearly dependent on temperature, with a positive coefficient of 0.3 per cent/K. This temperature dependence
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can be compensated by replacing resistor R1 with a temperature sensitive resistor, having a temperature coefficient closely matched to the scaling factor. Most diodes do not accurately obey equation 5.1. The derivation of this equation is based upon a single diffusion mechanism of current flow. There are actually several mechanisms operating and diode current is more accurately represented as the sum of several (N) components. The current components each have the form Ij Ioj (eqV/mjT – 1) j 1, 2, . . ., N where mj can take values between 1 and 4. A typical example of V/log(I) plots for generalpurpose silicon diodes is shown in Figure 5.7. The two straight lines in this case have slopes corresponding to values of m equal to 1.78 and 1.55.
Figure 5.7 Typical V/log(I) plot for a generalpurpose diode The resistance of bulk semiconductor material causes errors in the logarithmic relationship. The voltage across a diode is that across the junction and the internal resistance. At higher currents, the voltage drop across this resistance becomes significant, hence only a fraction of the total diode voltage appears across the junction. The above factors make generalpurpose diodes unsuitable for accurate logarithmic conversion, except over a restricted range (three decades of current at the most). Temperature compensation requires the selection of matched diodes (matched m factors), and this presents an added difficulty.
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Socalled ‘log diodes’ are available which are said to exhibit a 7decade current logarithmic range, but they are expensive. Transistors, which we will now consider, appear to be the most convenient elements for accurate logarithmic conversion. A bipolar transistor consists essentially of two interacting pn junctions; the circuit symbol and a simple model for an npn transistor are illustrated in Figure 5.8. The collector current of a transistor can be accurately represented by the equation Ic F IES (e–qVE/kT – 1) – ICS (e–qVC /kT – 1) –
I
CSj
(e–qVC/mjT – 1) (5.5)
where: F is the current transfer ratio between emitter and collector; it is very nearly unity, ICS is the collector reverse saturation current with the emitter shorted to the base, IES is the emitter reverse saturation current with the collector shorted to the base, mj is the ideality factor that takes on values between 1 and 2 for silicon transistors and up to 10 for III–V materials, and j is the number of the current path (1, 2, . . ., N).
Figure 5.8 Simple transistor model and sign conventions The sign convention adopted is shown in Figure 5.8. Equation 5.5 is appropriate for an npn transistor, the senses of VS and IS being reversed for a pnp device. The first term in equation 5.5 represents that part of the emitter current, comprised of minority carriers in the base, which diffuses to the collector. The second and third terms are analogous to the diode current equations (equations 5.1 and 5.4); they give the collector current for the emitter shorted to the base. The adoption of a circuit configuration which makes VC 0 causes all but the first term in equation 5.5 to become zero and the collector current is then given by the equation Ic F IES (e–qVE /kT – 1)
(5.6)
This is analogous to the ‘ideal’ diode relationship of equation 5.1. Note that the m ≠ 1 components of collector current become zero. The emitter (m ≠ 1) current components behave largely as majority carriers in the
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base and as such do not diffuse to the collector. IES is typically of the order 1013 A and F is very nearly unity. For values of collector current IC >> IES the exponential term in equation 5.6 predominates. Under these conditions, the following relationship holds: – VE 2.3
I kT log C q Io
(5.7)
where Io FIES. Note that F should not be confused with the commonly used grounded base current gain IC/IE. The value of F remains essentially constant over the range of collector currents for which equation 5.7 is valid. The VC 0 condition may be obtained by connecting the collector of the transistor to the summing point of an opamp, and the transistor base is connected to earth. This connection is made in the circuit shown in Figure 5.9. The circuit illustrates the socalled transdiode (Patterson diode) logarithmic configuration. The amplifier output terminal is connected to the emitter and provides the driving voltage (eo VE).
Figure 5.9 Logarithmic amplifier, transdiode configuration
The transdiode configuration of Figure 5.9 is capable of the widest range of logarithmic (log) conversion of input current. Accurate log conversion requires that F remain constant over a wide range of current values. Silicon planar transistors have this characteristic and can have a range of up to 10 decades. The upper end of the useful current range is determined by semiconductor bulk resistance effects and is usually between 1 mA and 10 mA. The earthed base used in the transdiode configuration has two disadvantages. It allows only single polarity input signals; the reverse polarity requires the use of a complementary transistor type. Also, the transistor has a frequency dependent gain and, since it is connected inside the feedback loop, this introduces closedloop stability problems. An alternative arrangement is illustrated in Figure 5.10. In this circuit the collector and base are connected together and the transistor acts as a diode.
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Figure 5.10 Log amplifier, diode connected transistor The circuit in Figure 5.10 is not capable of such a wide range as the transdiode circuit, but in many respects it is more versatile. Since it is a twoterminal device, its polarity can be reversed to allow a reversed input polarity. Several diodes may, if required, be connected in series for greater output voltages. Since the transistor produces no gain when connected as a diode, closedloop stability is achieved. In the diode configuration the feedback current (If) is not exactly equal to the collector current (IC). But, If IC IB IC(1 1/hFE) where IB IC/hFE is the base current drawn by the transistor and hFE is the common emitter DC current gain. Equation 5.7 becomes eo VE 2.3
kT log q
Ii F IES
1
(5.8) 1 hFE Transistors with a large value of hFE should be used in order to reduce the error term. The fall in hFE, which occurs at low current levels, sets the lower level of the input current at which the configuration departs significantly from logarithmic accuracy. The logarithmic range obtainable is typically within the range 103 A to 109 A. The curves illustrated in Figure 5.11 show the logarithmic characteristics of diode connected type 2N3707 transistors. The curves show the typical upper and lower limits of logarithmic range. A third transistor logarithmic configuration, which is sometimes used, is illustrated in Figure 5.12. The most useful feature of this connection is the reduced loading on the opamp output (only a small base current is required). Disadvantages of the circuit are the lack of reversibility, the separate supply for the collector, and a reduced logarithmic range. 1
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Figure 5.11 Logarithmic characteristics of diode connected transistors (type 2N3707)
Figure 5.12 Log amplifier, transistor connection The current fed back to the opamp summing point is the emitter current of the transistor (npn) which is given by equation 5.9. IE RICS(e–qVC /kT – 1) – IES(e–qVE /kT – 1) –
I
–qVE /mkT ESj(e
– 1) (5.9)
Where R is the reverse current gain of the transistor (R ~ 0.2). The collector is usually taken to a reverse bias of order 1 V. This gives Vc ≠ 0 and the first term in the equation contributes a small error. A more
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significant error is contributed by the mj ≠ 1 components of current represented by the third term of the equation. The useful logarithmic range with this configuration is typically within the range 105 A to 108 A.
5.4 Logarithmic amplifiers: practical design considerations
We will now look at practical considerations for logarithmic amplifiers. A more general treatment of practical considerations for opamp circuits is given in Chapter 9. The following are some of the more important points requiring attention in a practical logarithmic converter: (1) The designer must ensure closedloop stability. The method used to achieve this may affect the output slew rate, so this must be considered. (2) Offsets must be balanced out if the full capability of the opamp is to be exploited. The logarithmic range is usually determined by opamp offsets, rather than by the logarithmic range of the transistor. The relative importance of voltage and current offset is determined by the magnitude of the source resistance (see Chapter 2). (3) The transistor must be protected against possible damage caused by accidentally applying a reverse polarity voltage. (4) A means of temperature compensating the logarithmic transistor must be employed, unless the circuit is going to be used in a temperature controlled environment.
5.4.1 Closedloop stability Chapter 2 discussed amplifier stability. Stable (nonoscillatory) closedloop operation requires that the loop gain (AVOL) should be less than unity at frequencies where the phase shift around the loop reaches 180°. The condition implies that, on a Bode plot, the intersection of 1/ and AVOL should occur with a rate of closure of less than 40 dB/decade. In the feedback circuits considered so far we have assumed the feedback fraction to be determined by purely resistive components. This makes 1/ real at all frequencies and never less than unity. Under these conditions, an opamp openloop response characterized by a 20 dB/decade rolloff, down to unity gain, ensures closedloop stability for all values of input and feedback resistors. In practical circuits, the 20 dB/decade rolloff does not always ensure closedloop stability. Stray capacitance between the opamp’s summing point and earth causes a phase lag in the feedback fraction at the higher frequencies. This produces a corresponding phase lead in 1/. Capacitance at the opamp output can cause an additional phase lag. Both effects can lead to instability. The problem of stability in logarithmic amplifiers is further complicated by the nonlinear nature of the feedback. The feedback is greater, and therefore 1/ is smaller, at the higher input currents. In examining stability criteria, it is convenient to assume an opamp with a finite openloop gain with a 20 dB/decade rolloff down to unity gain. The effects of other departures from the ideal opamp are initially neglected.
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Since the feedback fraction is dependent on the operating current, we examine stability in terms of a smallsignal feedback ratio. The smallsignal feedback ratio ef /eo is assumed to be defined about some DC operating current IC. Referring to the circuit shown in Figure 5.13, the current fed back to the opamp summing point (If) is equal to the collector current of the transistor (IC).
Figure 5.13 Bode plot for transdiode configuration
Assuming a predominance of the exponential term in equation 5.6 we may write this equation as If F IES e–qeo /kT
(5.10)
Differentiating equation 5.10 with respect to eo gives the small signal feedback resistance rE. Thus And
If –qIf 1 –
eo kT rE rE
kT 1 qIf 40If
(5.11)
Note that for an operating current of 1 mA, the transistor’s intrinsic emitter resistance rE 25 , but when the operating current is, say, 1 nA, rE 25 M . A change in the output voltage eo results in a change in the feedback current If eo/rE. This in turn causes a change If Z1 in the voltage fed back
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to the opamp summing point. We may thus write the value of the smallsignal feedback ratio as
Z1/rE
(5.12)
Z1 is the impedance between opamp summing point and earth. In Figure 5.13, Z1 R1/(1 jC1R1) where C1 is the total capacitance between opamp summing point and earth. C1 is taken to include the capacitance between the collector and base of the transistor. The shunting effect of the collector output resistance is neglected. Substituting for Z1 gives 1/ rE(1 jC1R1)/R1
(5.13)
Note that, at the higher operating currents, it is possible for 1/ to be considerably less than unity (rE < R1). This feature is peculiar to the transdiode configuration; in other feedback circuits the lower limit of 1/ is unity. Remember that in the transdiode configuration the transistor acts as a common base amplifier for feedback signals and, as such, it can provide a voltage gain which is greater than unity. Values of 1/ for different operating currents are shown in Figure 5.13. For the purpose of the discussion, component values are chosen to simplify the arithmetic. The opamp is assumed to have a unitygain bandwidth product of 107/(2 ) Hz. We see immediately that the circuit fails to satisfy the closedloop stability criterion for operating currents greater than 1 A. One solution to the stability problem is to connect a capacitor C2 between the opamp output terminal and the summing point. This capacitor and rE cause a break in the Bode plot at an angular frequency 2 1/(C2rE). This causes attenuation in the value of 1/. But remember that the value of rE depends on the level of the operating current. The magnitude of C2 required to ensure closedloop stability at the higher operating currents places a severe restriction on the bandwidth and output slew rate at the lower levels of operating current. For example, to make 2 106 rad/s at an operating current of 1 mA requires a value of C2 equal to 0.04 F. This value of C2 makes 2 1 rad/s at an operating current of 1 nA, this has a time constant of 1 s. Another practical difficulty arises because of the finite openloop output impedance of the opamp. This inevitably causes a reduction in openloop gain when the amplifier is used to supply a low value load resistor. At an operating current of 1 mA, the transistor’s intrinsic emitter resistance is rE 25 ; such a small value is likely to have a marked effect on the gainbandwidth product of the amplifier. A remedy is to connect a resistor RE in series with the emitter of the transistor. In addition to reducing the loading on the opamp’s output, the introduction of RE allows the use of smaller values for C2. This in turn gives the system a wider bandwidth and an increased slew rate at the lower levels of input current. The arrangement is illustrated in Figure 5.14. Closedloop stability is again conveniently examined in terms of a smallsignal value of the feedback fraction . Referring to Figure 5.14,
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Figure 5.14 Bode plots for stable closedloop operation – If
eo jC2 (eo – ef) RE rE
ef is the feedback voltage developed between the amplifier summing point and earth. ef IfR1/(1 jC1R1) The smallsignal feedback ratio
ef /eo Manipulation of the above equations gives 1 R2 1 j (C1 C2) R1 R1 1 jC2R2
(5.14)
where R2 RE rE. The larger the value used for RE, the smaller is the value of C2 required to ensure closedloop stability at the higher operating currents. The Bode plot breakout frequency for 1/, 2 1/(C2R2) (at the higher operating currents) should be made to occur at least an octave before the intercept of 1/ with AVOL. The maximum value which may be used for RE is limited by the maximum output voltage swing of the opamp, bearing in mind that the maximum output voltage across the logarithmic transistor is approximately 0.6 V. Thus RE should be chosen so that
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Vo max 0.6 V > (IL max IC max)RE
(5.15)
The Bode plots in Figure 5.14 show values of 1/ obtained from equation 5.14. If the transdiode configuration is used for logarithmic scaling of current, R1 > and equation 5.14 becomes 1/ ≈ R2 j(C1 C2)/(1 jC2R2)
(5.16)
The Bode plots in Figure 5.15 show values of 1/, given by equation 5.16.
Figure 5.15 Bode plots, logarithmic current scaling In Figures 5.14 and 5.15, the smallsignal value of 1/ tends to the value 1 C1/C2 at high frequencies. In both cases the breakout frequency for 1/ at the higher operating currents is
2 ≈ 1/(C2RE) when RE >> rE A suitable choice for C2RE ensures closedloop stability at the higher operating currents. The use of the maximum value of RE allowed by equation 5.15 permits the smallest value of C2, and hence gives the fastest slew rate at the low current levels. The low current value of 2 is 2′ ≈ 1/(C2rE). In the diode configuration shown in Figure 5.16, the gain of the transistor is shorted out which means that 1/ cannot be less than unity. The circuit used with an opamp having a 20 dB/decade rolloff may be closedloop stable without the addition of a stabilizing network. If the simple circuit is
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not closedloop stable, it may be stabilized in the same way as the transdiode circuit. If a transistor’s operating current makes its value of rE less than the rated load of the opamp, a resistor RE connected in series with the emitter will be needed. The diode configuration Bode plots are illustrated in Figure 5.16.
Figure 5.16 Bode plots, diode configuration In the circuit shown the smallsignal value of 1/ is given by the relationship 1/ 1 Z2/Z1 where Z2 R2/(1 jC2R2), Z1 R1/(1 jC1R1) and R2 RE rE. Substituting for Z2 and Z1 gives 1
1
R2 j (C1 C2) R1 R1 1 j C2 R2
At high currents, (rE 15.4 mA, 5 mV/s
Chapter 9 9.4 5.6 m, 2.582 mV 9.5
100 k, 200 k
9.6
(a) 79 V, (b) 62 mV, (c) 95.34 mV
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Answers to exercises 303
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9.7
10 k, 10 k, 0.32 F, 7.95 nF
9.8
Ao 100, fo 159 Hz, Q 50.5, Rg 1 M, R7 1 M, R8 10 k, emax 0.1 V, R1 R2 796 k, R4 1.99 M
Chapter 10 10.1 0.013 pF 10.2 Refer to Figure 10.6, let Cp 4.7 pF 10.3 R3 5.1 M (a slightly lower value than this would be used in practice, say 4.7 M, in order to give a margin of adjustment) 10.4 R3 99 k, R5 690 k 10.5 2.45 V to 32.45 V, 4
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Appendix A1 Operational amplifier applications and circuit ideas The circuits given in this appendix represent extensions or modifications to the circuits given in the main body of the text. The reader conversant with the factors controlling accuracy and performance limitations (Chapters 2 and 9) should be able to use them as a basis for practical designs. Most circuits will function with a general purpose operational amplifier (use a BIFET) say) but the amplifier type used will inevitably govern performance limits. In all cases care should be taken to ensure that applied signals do not exceed allowable amplifier limits.
Scaling circuits
Figure A1.1 Adder–subtractor
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Figure A1.2 Differential input amplifier configuration with large common mode range
Figure A1.3 Current differencetovoltage conversion with variable scaling factor Signal sources
Figure A1.4 Voltage references
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Measurement and processing
Figure A1.5 Regulated voltage supply
Figure A1.6 Square wave generator with voltage control of pulse width (see Section 7.2.1)
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Figure A1.7 Square and triangular wave generator (see Section 7.2.1)
Figure A1.8 Positive ramp generator (see Section 7.2.1)
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Figure A1.9 Square and triangular wave generator with voltage control of frequency using a switched gain polarity amplifier (see Sections 7.4.3 and 8.12)
Figure A1.10 Twophase and triangular waveform generator with waveforms in quadrature (see Section 7.4.1)
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Figure A1.11 Sine, cosine and wave quadrature oscillator using phase shifter
Figure A1.12 Adjustable phase circuit for use with quadrature oscillator
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Figure A1.13 Phase shift oscillator with single resistor frequency control and zener amplitude stabilization
Figure A1.14 High input resistance AC voltmeter
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1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 Figure A1.16 Average 6 reading AC current meter 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 4911
Figure A1.15 Differential input, high input resistance AC voltmeter
Figure A1.17 Average reading AC current meter with current amplification
Figure A1.18 Measurement of high DC voltage with low reading voltmeter
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Figure A1.19 Resistance measurement, earthed resistor
Figure A1.20 Rate comparator
Figure A1.21 Simple window comparator
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Figure A1.22 Window comparator with control of window level and window width
Figure A1.23 Twoamplifier regenerative comparator with feedback bound and summing capability
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Figure A1.25 Ideal diode with current output
Figure A1.26 Single amplifier absolute value circuit for current input
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Figure A1.27 High input impedance absolute value circuit with variable gain
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Appendix A2 Gain peaking/damping factor/phase margin The closedloop gainpeaking and lightly damping transient response exhibited by closedloop configurations having an inadequate stability phase margin is in many cases due to the phase shift in the loop gain introduced by two break frequencies, one of which is remote (more than a decade away) from the other. Bode plots for commonly encountered situations are shown in Figure A2.1 and in both the cases considered the frequency dependence of the loop gain can be expressed by the relationship
Figure A2.1 Bode plots showing frequency dependence of loop gain
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AOL(jf) – j AOL(o) 
1
fc1
f 1 j f fc2
(A2.1)
( fc2 >> 10fc1) The closedloop signal gain of an opamp feedback circuit can be expressed in the form (see Section 2.3.1) ACL(f) ACL(o)
1 1 AOL(jf)
1
ACL(o) is the ideal frequency independent closedloop signal gain. Substitution for AOL(jf) and rearrangement give ACL(o)
ACL( jf) 1 j
f AOL(o) fc1
–
f
2
(A2.2)
AOL(o) fc1 fc2
Equation A2.2 represents the closedloop sinusoidal response. The more general closedloop transfer function is obtained in terms of the amplex variable s by the substitution, s jf, s2 f 2 giving ACL(o)
ACL(s) 1 j
s AOL(o) fc1
–
s
2
(A2.3)
AOL(o) fc1 fc2
Equation A2.3 represents a second order transfer function. Comparison with the general second order function 1 s2 1 2 s o o2 gives the relationships between the damping factor , natural frequency fo and amplifier parameters as T(s)
A2.1 Damping factor and phase margin
√ fc
2
2 √ ( AOL(o) fc1)
(A2.4)
and fo √ ( AOL(o) fc1 fc2)
(A2.5)
At the frequency f1 at which the 1/ and the openloop gain frequency plots intersect the magnitude of the loop gain is unity. Equation A2.1 gives the magnitude as
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A(jf) fc 1 AOL(o) 1 at f f1 f1
1
1
f1 fc2
2
(A2.6)
Combining equations A2.4 and A2.6 gives
1
(A2.7) f1 f 2 1/2 1 1 fc2 fc2 Phase margin is related to f1 and the break frequency fc2 by the relationships 2√
1 f1 ; 1 fc2 tan m
ff
2 1/2
1
c2
1 sin m
(A2.8)
( fc2 >> fc1) Substitution in equation A2.7 gives the relationship between damping factor and phase margin as
2√
1 cos m sin2m
(A2.9)
Gain peaking The magnitude of the closedloop signal gain is, from equation A2.2 ACL(jf)
ACL(o)
(A2.10) f 2 f 2 2 2 √ 1– f fo o where and fo are determined by equations A2.4 and A2.5. The magnitude peaks for < 1/√2 and the frequency at which the gain peak occurs can be found by differentiating equation A2.10 with respect to f and equating to zero. This gives the frequency at which the gain peak occurs as
fp fo √(1 22) (For < 1/√2)
(A2.11)
Substituting this value of fp in equation A2.10 gives ACL(jf) ACL(o) at peak 2 √ (1 – 2)
(A2.12)
The extent of the magnitude peaking may be expressed as P(dB of peaking) 20 log10
1 2 √ (1 – 2)
(A2.13)
The relationship between gain peaking and phase margin may be obtained by substituting the value of from equation A2.9, thus
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P(dB of peaking) 20 log10
2 cos m sin2 m cos m –1 4 2 sin m
√
(A2.14)
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Appendix A3 Effect of resistor tolerance on CMRR of one amplifier differential circuit In Figure A3.1 the amplifier is assumed ideal, resistors have tolerance 100 per cent per cent and worst case CMRR is considered. An input common mode signal ecm gives rise to an output signal
Figure A3.1 CMRR due to resistor tolerance with worst case distribution eocm ecm
R (1 – x)R (1 –Rx)(1 x) R (1 – x)R (1 –Rx)(1 x) 2
1
2
–
R2 (1 x) R1 (1 – x)
1
2
1
ecm
R2 R1 (1 – x) R2 (1 x) 1 x – R1 R2 (1 – x) R1 (1 x) 1–x
ecm
R2 R1 4x R1 R2 (1 – x)2 R1 (1 x2)
ecm
R2 4x R1 R1 R2 R1
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Thus common mode gain eocm ecm
R2 4x R1 R1 R2 R1
R2 R1 differential gain and CMRR common mode gain R2 4x R1 R1 R2 R1 1 CMRR
A3.1 CMRR of one amplifier differential circuit due to noninfinite CMRR of operational amplifier
R2 R1
(A3.1)
4x
Common mode signal applied to opamp ecm
R2 R1 R2
(see Figure A3.2)
Noninfinite CMRR of an opamp is represented by an equivalent input error signal e cm applied directly to the input terminal of the opamp
Figure A3.2 CMRR of circuit due to noninfinite CMRR of amplifier
R2 R1 R2 CMRR(A)
ecm e cm
e cm gives an output signal
eocm e cm 1
R2 R1
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Thus, common mode gain of circuit
eocm ecm
R2 R1 CMRR(A)
and CMRR of the circuit differential gain/common mode gain CMRR(A).
A3.2 Overall CMRR due to resistor mismatch and noninfinite CMRR of operational amplifier
Effects of resistor tolerance and CMRR(A) are represented by separate input error generators (Figure A3.1). Output signal eocm due to input signal ecm is eocm ecm
1 CMRR
(R)
±
1 A CMRR(A) diff
Overall CMRR
differential gain common mode gain
CMRR(R) CMRR(A) CMRR(A) ± CMRR(R)
Adiff 1 1 ± A CMRR(R) CMRR(A) diff
(A3.2)
Ideal differential amplifier circuit with infinite CMRR
Figure A3.3
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Appendix A4 Instrumentation transducers A4.1 Introduction
Because the ‘front end’ of an instrumentation system frequently consists of one or more sensors, the purpose of this appendix is to give the reader a brief introduction to these devices which often provide the input signal to opamps. Most instrumentation systems comprise three basic sections: one for sensing the measurand, the next for conditioning the sensed signal and finally one for displaying or recording the conditioned signal. Figure A4.1 shows the block diagram of this arrangement. The sensing element, known as a sensor or transducer, simply converts one form of energy into another. In this appendix all the transducers considered produce an electrical output when stimulated. However, the transduced electrical output may be of insufficient power and require amplification or other modification before it can be displayed or recorded. The necessary amplification, shaping, mixing or other such processing is undertaken in the signal conditioning section using the techniques variously described elsewhere in this book. Finally, the conditioned signal is recorded or displayed. A simple example of the above basic system is that of a tank containing a hot liquid, the temperature of which needs to be monitored and recorded continually. The temperature sensing element could be a thermocouple (described later), the electrical output of which is conditioned by an opamp to raise it to the necessary power level required to drive a chart recorder. The remainder of this appendix will describe some of the more popular transducers used with instrumentation systems and will not consider signal conditioning or display and recording techniques.
Figure A4.1 Block diagram of basic instrumentation system
A4.2 Resistance strain gauges
These are devices which when subjected to mechanical strain are deformed, within their elastic limit, and change their ohmic resistance. The strain gauge therefore is most suitable for detecting and measuring small mechanical displacements. The strain gauge is firmly secured to the test piece which when strained under load causes the attached strain gauge also to distort.
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The strain gauge is usually part of an initially balanced resistive bridge network (see Chapter 8) and the accompanying change of gauge resistance causes an imbalance and an output signal from the bridge indicative of the amount of strain in the workpiece. Figure A4.2 shows typical foil type strain gauges used for general engineering strain analysis. The strain gauge measuring grid is manufactured from a copper nickel alloy which has a low and controllable temperature coefficient. The actual form of the metal grid, which changes its resistance under strain, is accurately produced by photoetching techniques. A thermoplastic film is used to encapsulate the grid which helps to protect the gauge from mechanical and environmental damage. It also acts as a medium to transmit the strain from the test piece to the gauge material. The principle of operation of this device is based on the fact that the resistance of an electrical conductor changes with a ratio of R/R if a stress is applied such that its length changes by a factor L/L. This is where R is the change in resistance from the unstressed value R and L is the corresponding change in the unstressed length L.
Figure A4.2 Typical foil strain gauges The change in resistance is brought about mainly by the change in physical size of the conductor and, because of changes in its physical structure, an alteration in the conductivity in the material. Copper nickel alloy is commonly used in the construction of strain gauges because the resistance change of the foil is virtually proportional to the applied strain, i.e. R/R K . E where K is a constant known as the gauge factor and E is the applied strain. Therefore R/R gauge factor L/L The change in resistance of the strain gauge can thus be utilized accurately to measure strain when connected to an appropriate measuring and indicating circuit.
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Strain gauges are available commercially in a wide variety of preferred sizes and specifications. However, a typical specification for a small foil type strain gauge is as follows: Measurable strain Thermal output at 20–160°C at 160–180°C Gauge factor change with temperature Gauge resistance Gauge resistance tolerance Fatigue life Foil material Temperature range Gauge length Gauge width Gauge factor Base length (single types) Base width (single types) Base diameter (rosettes)
2 to 4% maximum ±2 strain/°C* ±5 strain/°C* ±0.015%/°C max. 120 ±0.5% 105 reversals at 1000 strain* copper nickel alloy 30°C to 80°C 8 mm 2 mm 2.1 13.0 mm 4.0 mm 21.0 mm
* 1 strain is equivalent to an extension of 0.0001%. While the strain gauge is basically a displacement type transducer, because strain is caused by force the gauge can readily be adapted to measure force, torque, weight, acceleration and many other quantities. It should be noted that because the resistance of strain gauges is affected by changes in the temperature, they are often used in pairs; one in each of the balancing limbs of the measuring bridge circuits. Only one gauge is fixed to the test piece to act as the sensor, the other, being connected into the balancing limb of the bridge, is alongside but not fixed to the workpiece and is purely for temperature compensation purposes. Figure A4.3 illustrates this connection. Also, because the strain gauge resistance is quite low, typically 120 , the remote connection of a sensor gauge away from the instrumentation bridge circuit can cause problems. This is because the resistance of the long connecting leads may have significant resistance compared with that of the sensor gauge itself. The problem can be overcome using three connecting leads to the remote sensor gauge as shown in Figure A4.4. The extra lead is connected so as effectively to place two equal resistance connecting leads in series with each of the bridge limbs AC and DC without disturbing the electrical balance.
A4.3 Platinum resistance temperature detectors
Like strain gauges, these are passive transducers which change their resistance when stimulated. They are also known as resistance thermometers because they suffer a change of resistance with change of temperature. The change of resistance can be detected using similar bridge circuits and opamp conditioning circuits as are used with strain gauges. The voltage output from these circuits is calibrated to indicate temperature.
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Figure A4.3 Strain gauge bridge circuit with temperature compensation included
Figure A4.4 Threewire compensating lead connection The resistive element is made from platinum because not only does this metal exhibit a near linear variation of resistance with temperature change, it also shows a large (38.5 per cent) change of resistance for a 100°C temperature change. The platinum temperature sensing element is usually sheathed for protection and may be mounted in a variety of probes, some being handheld. The platinum thermometers can be very accurate and typically are manufactured to conform to BS 1904 Grade 2 and DIN 43 760. A typical specification is as follows: Resistance at 0°C Temperature coefficient Maximum temperature Minimum temperature Resistance tolerance at 0°C at 500°C
100 ± 0.1 0.385 /°C 500°C 50°C ±0.2 (±0.3°C) ±0.8 (±2.4°C)
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Platinum resistance thermometers can be manufactured to give very accurate and longterm stable readings. They are often employed as laboratory temperature standards and where accurate temperature control is required. However, they can be fragile and have a slow response time of up to a second.
A4.4 Thermistors
These are devices which may have positive or negative temperature coefficients (ptc or ntc). They are manufactured from semiconductor materials and are often packaged as small discs, some 5–12 mm in diameter, or at the tip of a probe. The principle of operation of the thermistor is that its resistance changes with temperature. However, unlike the platinum resistance thermometer, the resistance: temperature relationship of the thermistor is very nonlinear and its upper working temperature is usually much lower. The thermistor is quite robust, especially in disc form, and its small size and sensitivity make it very suitable for the temperature control of ovens, deep freezers, rooms, process control, temperature compensation, high temperature protection, high current protection and the like. But, because of its nonlinearity and fairly wide tolerances, care should be taken to check the calibration of circuits after a thermistor change has been made. A typical specification is as follows: Resistance at 25° at 125°C Maximum temperature range Maximum dissipation Thermal time constant
A4.5 Pressure transducers
10 k 260 30°C to 125°C 900 mW 30 s
There are several designs available and the purpose of each is to convert a fluid pressure into an analogous electrical signal. Some designs have a diaphragm which is moved by the measurand pressure and this movement is translated into a change of resistance, inductance or capacitance. Other pressure transducers use the piezoresistive effect. Advanced manufacturing techniques include laser trimmed bridge resistors for close tolerance on null and sensitivity. The sensing element is a 0.1 inch square silicon chip with integral sensing diaphragm and four piezo resistors. When pressure is applied to the diaphragm it is caused to flex, changing the resistance, which results in an output voltage proportional to pressure when a suitable excitation voltage is applied to the device. The sensing resistors are connected as a fouractive element bridge for best linearity and sensitivity. A typical technical specification for one of these transducers are as follows: Pressure range Full scale output Sensitivity/psi Excitation Overpressure
0–30 psi 79 mV 2.63 mV 10 V DC 60 psi max.
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A4.6 Thermocouples
These are active transducers which convert the difference between two temperatures into a proportional voltage. The thermocouple principle is based upon the Seebeck effect which is simply the generation of a voltage by a heated junction of dissimilar metals. Figure A4.5 shows how a couple of two such metal junctions, at different temperatures, can be connected to cause a meter to indicate the voltage potential between the two junctions. One junction, the ‘cold’ or ‘reference’ junction, is usually held at 0°C (although room temperature suffices for some applications) while the other junction is used as a ‘temperature sensor’.
Figure A4.5 Principle of thermocouple action The metals used include nickel, chromium, iron, platinum, rhodium, aluminium, constantan, manganese and silicon. Most thermocouple manufacturers use different pairs of these metals, or their alloys, to produce a selection of small, robust devices capable of measuring temperatures ranging from 230°C to 1300°C. To indicate their designed temperature ranges and other characteristics, thermocouples are usually classified as being Type J, K, N or T. However, because the thermocouple sensor junction is placed in physical contact with the measurand, for temperatures above 1300°C, which is higher than the freezing point of most metals, optical pyrometer temperature measurement becomes more appropriate. The device usually comprises two metres of thermocouple wire insulated with varnishimpregnated glass fibre sleeving having an overall diameter of 1.5 mm. The hot junction tip is welded in an argon atmosphere to eliminate any oxidization of the junction. It has an operating range of 50°C to 400°C. Its small size and flexibility make it suitable for temperature measurement in confined places such as electronic assemblies. A high quality handheld probe can be used not only for general purpose temperature measurements in the range 100°C to 600°C by, say, immersion in liquids, but also because of its sharpened stainless steel probe tip and robust construction it can penetrate solids for internal temperature measurements. This makes it ideal for use in the food industry for checking the temperature of frozen foods, or for general measurement of belowsurface temperatures of soil, grain, and powders.
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A4.7 Linear variable differential transformers (LVDT)
A miniature AC energized LVDT is one of a range of the most common forms of displacement transducer. LVDTs typically comprise three coils wound inline on an insulating hollow former inside which is a movable nickel iron core. The centre of the three coils is energized by an alternating current and, with the movable core in the centre position, induces equal emfs across the other two coils which effectively form the secondary windings of a transformer. Movement of the core disturbs the balance of the magnetic coupling between the three coils. By comparison of the now unbalanced secondary coil output voltages, the magnitude and direction of the core movement can be determined. The displacement to be measured is applied to the movable core and because it has no direct sliding contact is virtually friction free. This gives the LVDT an advantage over the resistive potentiometric transducer which is sometimes used in similar applications. The LVDT can be used to detect movements in the range 0.5–25 mm.
A4.8 Capacitive transducers
These are passive displacement transducers which also require an AC excitation. A basic capacitor comprises a pair of parallel metal places between which is either a space or a solid dielectric material in which energy is stored when a voltage is applied between the plates. The capacitance, in farads, of a device is a measure of its ability to store this energy and depends upon the area of the plates, their spacing and the nature of the dielectric. The mechanical variation of any one of these three parameters will cause a sympathetic variation in the capacitance of the device. Since the spacing between the plates of a capacitor is usually less than 1.0 mm, a very detectable 10 per cent variation in capacitance requires a change in the plate spacing of less than 100 microns. This sensitivity makes the capacitive transducer one of the most suitable sensors for the measurement of small displacements.
A4.9 Tachometers
These are used for the measurement of shaft angular velocity and are available in two basic types: Pulse tachometers. These have a toothed ferromagnetic disc which must be coupled to and rotated by the shaft, the speed of which is to be measured. The ferromagnetic disc may be manufactured with only a single toothlike protrusion which is arranged to fall close to a pickup head once in each revolution of the disc. The pickup head comprises a permanent magnet around which a coil is wound. The passage of the tooth through the magnetic field causes a distorting movement of the field and this flux movement induces an emf across the pickup coil. The number of pulses counted or the average DC produced in a given time from a train of these pulses is indicative of the shaft speed. Tachogenerators. These are really no more than either DC machines which produce a direct voltage proportional to their angular velocity or AC alternators which have a direct relationship between their speed of rotation and their output frequency.
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A4.10 Electromagnetic flowmeters
Figure A4.6 shows the typical layout of an electromagnetic flowmeter as used for measuring the rate of flow of a wide range of liquids. The basic principle involved is that of a current being induced into a conductor which is moving through a magnetic flux. In this case the moving conductor is the fluid itself and the magnetic flux is produced by external excitation. The fluid must have a resistance per cm3 of less than 10 M to permit the generation of a satisfactory signal (domestic tap water has a resistance per cm3 of about 50 k ). The moving fluid is contained within a smoothbore plastic pipe into which two pickup electrodes are inserted and which collect the current generated, it being proportional to the rate of fluid flow.
Figure A4.6 Principle of electromagnetic flowmeter
Electromagnetic flowmeters are available commercially with diameters ranging from 3 mm to 2000 mm. They have been used successfully to measure the flow of tap water, sea water, mercury, blood, chemicals and, because of the use of smoothbored pipes, slurries and liquids containing solids.
A4.11 Hall effect transducers
Figure A4.7 shows how a currentcarrying conductor situated in a perpendicular magnetic field experiences a transverse voltage which is proportional to the product of the current and the magnetic field flux density. The voltage so established is present in all conductors but is of particular significance in semiconductor materials. It can be shown that the current, I the flux density, B, and the voltage generated, E, are related by the expression: E RH(I B) RH is known as the Hall coefficient and is given by 1/ne where n is the number of charge carriers per unit volume which constitute the current and e is the charge on the carriers.
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Figure A4.7 The Hall effect The Hall effect voltage in semiconductors in the presence of a magnetic field is used to produce ‘bouncefree’ switching. A switched transistor is turned on by a Hall effect device under the influence of a magnetic field exceeding a designed ‘operate’ strength. However, the Hall effect device does not ‘release’ until the magnetic field strength is reduced to a level below the operate level. It is this hysteresis effect that produces the ‘bouncefree’ switching. The Hall effect vane switch transducer makes use of bouncefree switching in its operation of transducing the presence of a ferrous metal into an electrical signal. A Hall effect sensor and magnet are housed in a pcb mounting package which will detect the presence of a ferrous metal vane passing through the gap between the sensor and the magnet. The device, which operates from 5 V direct (7 mA quiescent current), features two independent TTL compatible outputs capable of sinking up to 4 mA each or 8 mA combined. The switching time is less than 3 s and the operating frequency can be up to 100 kHz. The device is useful in many position or counting operations, particularly in dusty or high ambient light environments, where an optical switch would be unsuitable. The miniature linear Hall effect IC is a magnetic field sensor in a moulded 4pin dil plastic package less than 8 mm square. This device features a differential output stage. One output increases linearly in voltage, while the other decreases, for a linear increase in magnetic flux density over a ±40 mT range. Typically, the output voltage varies linearly between 1.0 V and 3.0 V with a sensitivity of 1.0 mV/Gauss. Typical applications for this device include the investigation of magnetic fields in the vicinity of transformers and cables and as current sensors with high isolation and in linear feedback elements in analogue control systems. The sensor is immune from damage by high values of flux density.
A4.12 Opto transducers
Opto transducers are devices which change one or more of their electrical characteristics when struck by light. The light is not necessarily visible to the human eye; it may be infrared. Outlined below are brief details of a small selection of the many opto devices available commercially. The light dependent resistor (LDR) uses a small strip of cadmium sulphide which may be illuminated by light passing through a clear window in the
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casing of the device. The resistance of this particular device can vary from about 500 in bright sunlight to 1.0 in darkness. It can be used at mains voltages (320 V DC or AC peak), it is cheap and sensitive but can have a slow response time of 120 ms. Typical applications for the LDR are the automatic control of public lighting, in intruder sensing devices and reflective smoke alarms. All silicon diode junctions are affected by incident light and the photodiode is little more than a conventional silicon diode placed in a casing which is fitted with a window to allow the diode junction to be illuminated. The leakage current of the diode is very small but this increases when the junction is struck by light. The photodiode is operated in a reversed bias mode and in series with a load resistor through which the light dependent leakage current flows. The voltage drop across the load resistor is analogous to the intensity of the light striking the photodiode. Compared with the LDR, the photodiode is similarly packaged, will not operate with such high supply voltages, is not as sensitive to light stimulation but its response is much faster, being in the order of a few microseconds. Typical applications for photodiodes are in fast response AC circuits, in infrared beam switching and with photographic flash circuits. The phototransistor operates in much the same way as the photodiode, the basecollector junction being effectively reverse biased and stimulated by light. However, the amplifying effect of the transistor makes the sensitivity of this device more than ten times that of the photodiode. But it cannot operate at such high frequencies; typically up to 200 kHz rather than the 500 MHz of the photodiode. Optical shaft encoders are now available for sensing shaft position or angular velocity. Typically, these devices are 50 mm long and 50 mm wide and 50 mm in diameter and contain a light source beamed through a perforated rotating disc and detected by a light sensor. Rotation of the input shaft causes the energized encoder to produce an output comprising a number of TTL compatible pulses for each complete revolution. The device typically requires a DC excitation of 5–30 V and, depending upon the specification chosen, will provide resolutions of 100, 1250, 2000 or 2500 pulses per revolution. Typical applications are in machine tool control, robotics and position sensors for feedback on mechanical valve openings.
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Bibliography [1] Terrell, Op Amps: Design, Application and Troubleshooting, 1996 (ButterworthHeinemann) ISBN 0–7506–9702–4 [2] Graeme, Optimizing Op Amp Performance, 1997 (McGrawHill) ISBN 0–07–024522–3 [3] Dostal, Operational Amplifiers, 1993 (ButterworthHeinemann) ISBN 0–7506–9317–7 [4] Texas Instruments, Linear Design Seminar Slide Book, 1992 (Texas Instruments) SLYZE01. [5] Texas Instruments, Linear Mixed Signal Design Seminar Reference Book, 1994 (Texas Instruments) SLY6E03. [6] National Semiconductor, 1999 Analog Seminar Reference Book, 1999 (National Semiconductor) Literature Number 570141–004. [7] Various Application Notes from Texas Instruments, National Semiconductors, Maxim, Analog Devices [8] Various magazine articles from Electronics World, Electronic Engineering, EDN, [9] Horowitz and Hill, The Art of Electronics, 1989 (Cambridge University Press) ISBN 0–521–37095–7 [10] Graf, Amplifier Circuits, 1997 (ButterworthHeinemann) ISBN 0–7506–9877–2 [11] Hickman, Electronic Circuits, Systems and Standards, 1991 (ButterworthHeinemann) ISBN 0–7506–0068–3 [12] Hickman and Travis, EDN Designers Companion, 1994 (ButterworthHeinemann) ISBN 0–7506–1721–7 [13] Savant, Roden and Carpenter, Electronic design: Circuits and Systems, 1991 (Benjamin Cummings) ISBN 0–8053–0285–9 [14] Winder, Analog and Digital Filter Design, 2002 (Newnes) ISBN 0–7506–7547–0.
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Index 555 Timer, 192–4 8038 Waveform generator, 195–8 Absolute value circuit, 314–5 AC amplifiers, 106 AC voltmeter, 310–1 Acquisition time, 217 Active filters, 237–65 Adder, 5, 25 Adder subtractor, 6, 304 Allpass filter, 252–3 Amplifier symbol, 1 Analogue to digital converter, 220–3 Answers to exercises, 300–3 Antilogarithmic converter, 137–41 Aperture time, 216 Astable, 175, 192–4 Averaging, 257–8 Balancing offsets, 45, 48, 129 Bandgap voltage reference, 297 Bandpass filter, 234–6, 248–51 Bandstop filter, 236, 251–2 Bandwidth, 20, 74, 77, 82–4, 135, 165, 231 Battery powered, 69, 72 Bessel response, 246 Bias current, 45, 66, 69, 82, 95 BiCMOS opamp, 64, 69, 70 BiFET opamp, 11, 64, 70 Binary weighted DAC, 224–6 Bipolar opamp, 11, 64, 70 Bode approximation, 20–1, 232, 234 Bode plots, 19, 25, 122, 124, 204 Bootstrapping, 107 Break frequency, 20, 231 Bridge amplifier, 200–3 Buffer, 6, 75, 83 Butterworth response, 241, 243–4 Capacitance loading, 26, 80, 275 Capacitance multiplier, 181–2 Capacitive transducers, 203, 329 Capacitors, 281–2 Cauer (or Elliptic) response, 245
Chebyshev response, 244–5 Chopper stabilisation, 66 Closed loop bandwidth, 19 Closed loop gain, 3, 16–8, 22, 64 Closed loop stability, 25, 77, 93, 121, 135 CMOS opamp, 11, 68, 70 Common mode error, 49 Common mode input impedance, 90 Common mode rejection ratio (CMRR), 49, 66, 80, 89, 320 Common mode voltage, 13 Comparators, 171, 312–3 Compensation, 28, 77 Complementary bipolar technology, 65 Composite amplifier, 287 Constant current, 297–8 Current adder, 5, 98 Current booster, 284 Current feedback, 63, 73–81 Current limiting, 104 Current measurement, 97 Current mirror, 74 Current scaling, 93 Current sink, 102–3 Current source, 94, 99–103 Current summation, 5, 98 Current to voltage converter, 5, 93, 98, 305 Cutoff frequency, 231, 241 Damped response, 40, 233, 316 Decibel (dB), 19 Decoder based DAC, 224 Depletion MOSFET, 105 Dielectric absorption, 216–7, 282 Differential input, 12, 92, 157–8, 168–9 Differential input amplifier, 1, 88–93, 305 Differential signal transmission, 199 Differentiator, 163–8 Digital to analogue converter, 223–8 Diode connected transistor, 119 Diode limiting, 174, 283 Diode transfer function, 110
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384 Index
1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 49111
Divider, 139 Drift, 45, 70, 149, 280, 289 Earth loop, 271 Earthed load, 100–2 Electromagnetic flowmeter, 330 Electrostatic discharge (ESD), 69 Evaluating errors, 46 Excalibur, 65 Feedforward frequency compensation, 34 Feedback, current, 63, 73 Feedback, negative, 2, 13 Feedback, positive, 173 Feedback, voltage, 14–8, 63–4 Field effect transistor (FET), 185 Filters, active, 77, 237 Filters, passive, 230 First order lag response, 20 Floating load, 100 Follower, see buffer Frequency compensation, 28, 39 Frequency dependent negative resistance (FDNR), 259–62 Frequency response, 19, 22 Frequency to voltage converter, 218–20 Fullpower response, 44 Fullwave rectifier, 211–3 Function generator, 195 Gain, 13 Gain bandwidth product, 24 Gain error factor, 27, 77 Gain peaking, 27, 318 Guarding, 273 Gyrator, 238, 262–5 Halfpower bandwidth, 20 Hall effect, 208, 330 High input impedance, 107 High pass filter, 234, 246–8 High voltage regulator, 105–6 Hold time, 214–8 Hold mode, 147 Hotwire anemometer, 205 Hysteresis, 173, 313 Ideal amplifier, 2 Ideal diode, 114, 314 Inductive loads, 100 Input bias current, 45, 67–8 Input capacitance, 77, 181, 203–4, 274–6
Input impedance, 14, 18, 64, 69, 76, 90, 150 Input offset current, 45 Input offset voltage, 45, 67 Input resistance, 84 Input voltage limits, 12 Instrumentation amplifier , 92 Instrumentation transducers, 323–32 Integrated circuit, 8, 63 Integrating AtoD converter, 221 Integrator, 7, 78, 146–63 Integrator reset, 160–2 Interface circuit, 199, 203 Interference, 272 Inverter, 2, 17, 82, 106 JFET input opamp, 64, 67, 71 Lag compensation, 37 Laglead network, 34–7 Large signal settling time, 44 Lead compensation, 36 Light dependent resistor, 331–2 Limitation of gain, 13 Limitations of input, 11, 13 Limitations of opamps, 8 Limitations of output, 12 LinCMOS opamp, 63, 70 Linear circuits, 82 Logarithmic amplifier, 109–45 Longtailed pair, 11 Loop gain, 16, 74 Low dropout (LDO) regulator, 105 Low pass filter, 230–3 Magnitude, 20 Modulation, 197 Monostable, 178, 194 MOSFET, 68–9, 161 Multiplier, four quadrant, 141 Multivibrator, 175 Negative impedance conversion (NIC), 237 Noise characterisation, 50, 71, 78 Noise current, 64, 67, 79 Noise density spectrum, 52 Noise figure, 58 Noise gain, 84, 166 Noise voltage, 65, 67–8, 71, 79 Nonideal amplifier, 14 Noninverting amplifier, 83, 106 Nonlinear response, 50, 109
AMPLIFIERS 15 Ind 2/6/03 7:33 PM Page 385
Index 385
1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 4911
Normailzation and scaling, 253–5 Notch filter, 236, 251–2 Offset balancing, 45, 129, 277–80 Offset errors, 45, 66, 88, 95, 127, 149, 166 Openloop gain, 13, 20 Openloop transfer curve, 12 Oscillators, 183, 306–10 Output current boosting, 284 Output impedance, 14 Output level biasing, 287–9 Output voltage boosting, 284–7 Output voltage range, 12 Over temperature shutdown, 104 Overload recovery, 44, 282 Overshoot, 42 Packages, 8 Passive filters, 230 Passive Filters band reject (notch) filter, 236 Peak detector, 213–5 Peaktopeak detector, 216 Peaktopeak noise, 52 Peaking, 27, 41 Phase, 20 Phase compensation, 28 Phase inversion, 65 Phase margin, 27–30, 317 Phase shift, 77, 232 Phase shifting circuit, 252–3, 309 Phasefrequency response, 26 Photodiode sensor, 208, 332 Pink noise, 53 Positive feedback, 173 Power supply, 72, 80, 276–7 Power supply bypassing, 81, 270, 276 Precise diode circuits, 209–11, 314 Pressure transducer, 327 Protection circuits, 12, 129–30, 282 Quadraturephase oscillator, 185, 309 Quiescent current, 68 Ramp generator, 190, 307 Rate comparator, 173, 313 Recovery time, 44 Rectifier circuits, 209–13 Reference voltage, 295–7 Regenerative comparator, 173, 313 Regulated voltage supply, 293, 306 Resistance measurement, 312 Resistance strain gauges, 323–5
ResistiveT network, 84, 96 Resistors, 281 Ringing, 41 Rise time, 39 RMS converter, 139 Rolloff, 21 Run mode, 147 SallenKey filters, 77, 255–7 Sample and hold circuits, 215–8 Schmitt trigger, 173, 313 Sensor interfacing, 199 Series voltage feedback, 15 Set mode, 147 Settling time, large signal, 44, 78 Settling time, small signal, 43 Shielding, 273–4 Signaltonoise ratio, 55 Sine wave oscillator, 183 Single supply operation, 291–3 Slew rate, 33, 43, 67, 69, 76, 79, 155 Slew rate errors, 155 Small signal response, 38 Small signal settling time, 43 Square wave generator, 187, 306–8 Stability, closed loop, 25, 77, 80, 93, 121, 135, 275 State variable filter, 248–51 Step response, 40–2 Strain gauge, 323–5 Subtractor, 6, 88 Successive approximation AtoD, 222–3 Summation, 5, 87–8, 156, 174 Summing point, 2, 79, 109 Supply voltage sensitivity, 46 Switched gain, 86 Symbol, 1 Temperature drift, 46, 130, 137, 295–6 Temperature effects, 70, 93 Thermistor, 327 Thermocouple, 206–7, 328 Thermometer code DAC, 227–8 Time averaging, 257–8 Timer circuit, 192 Transconductance, 34, 141–3 Transdiode, 118 Transducer, 203 Transfer curve, 12 Transfer function, 63–4, 231 Transient response, 37 Transimpedance, 63–4, 73 Triangular wave generator, 187, 195, 307–8
AMPLIFIERS 15 Ind 2/6/03 7:33 PM Page 386
386 Index
1111 2 3 4 5 6 7 8 9 1011 1 2 3 4 5 6 7 8 9 20111 1 2 3 4 5 6 7 8 9 30111 1 2 3 4 5 6 7 8 9 40111 1 2 3 4 5 6 7 8 49111
Unity gain follower, 6, 76, 83 Unity gain frequency, 23, 77 Variable gain, 85 Virtual earth, 3, 5 Virtual ground generator, 294–5 Voltage adder, 5 Voltage booster, 284–7 Voltage controlled gain, 86 Voltage controlled oscillator, 306 Voltage feedback, 14–8, 63–4, 69
Voltage Voltage Voltage Voltage Voltage
reference, 104, 295–7, 305 regulator, 103, 293–4, 306 summation, 87–8 to current converter, 6, 99 to frequency converter, 218
Waveform generators, 187 White noise, 52 Wideband circuits, 73, 269 Wien Bridge, 184 Window comparator, 312–3